# Focused sprite DMA comparison

Run `bash tests/sprites/run.sh`. The test connects real Agnus arbitration,
sprite DMA, Gary, the SRAM bridge and Denise. A long A-to-D Blitter copy
runs throughout sprite fetching; a direct CPU register driver uses the
normal Blitter slowdown request to write BPL1DAT on each displayed line.

Four cases compare normal/turbo Blitter scheduling at ordinary vertical
positions and with VSTART/VSTOP crossing line 255. Each case checks all
eight channels, 94 DMA words, pointer increments, POS/CTL versus DATA/DATB
destinations, captured words, and 2,910 scanout samples against a reference.
The image heights vary from three to five lines, including the last image
row and stop-line control fetch. All 94 sprite transfers occur while the
Blitter is busy.

On R3 `f500976`, all four cases pass with signature `23a8e1e8`. Turbo raises
the competing Blitter grant count from 2,578 to 5,281 without changing
sprite transfers or scanout. No turbo sprite arbitration fault was
reproduced. The initial run is recorded in `build/r3-sprite-dma.log`.

## Limits

Beam positions and a header-fetch blanking interval are supplied by the
test, including a synthetic header fetch before the scene near line 255.
This isolates vertical-bit decoding; it does not test a full PAL frame or
real vertical-blank timing. The unreset sprite scan selector starts at
zero to model FPGA configuration. SRAM access/pad/return delays are
30/10/10 ns assumptions, not measured board timing.

The runner uses ECS and unattached sprites, nonoverlapping sprite/Blitter
memory, and no Copper, audio, disk or bitplane DMA. BPL1DAT enables Denise
sprite output, but final palette/RGB compositing is outside the checks.
It does not test CPU/Copper updates to sprite pointers during active DMA,
simulate a game, or establish whether Toki draws the character with
hardware sprites. Passing this comparison does not exclude a software
timing issue or another rendering path.
