# SPI bridge regression

Run `bash tests/mia/run.sh`. Requires Icarus Verilog, Python 3 and the original
repository commit `a8c27a167cec5598fd439cbbef11ea1591d09c90` (`BASELINE_REV` can
override it).

The test drives actual serial clock/data/select pins into both implementations
and compares the physical SRAM address, data, both write strobes, bus request,
reset and busy outputs on each chipset-clock cycle. The default run uses the
production Mia clock of 7.09 MHz with asynchronous 10 MHz SPI and a 600 ns header
word gap. Payload writes stream continuously with no interword gap. A second run
uses a 60 MHz bridge clock and 120 ns header word gap as an additional
stress configuration; production uses 60 MHz only for the CPU, not Mia.
`HALF_CORE`, `WORD_GAP` and `DATA_WORD_GAP` control the simulation clock and gaps.
No internal state is forced.

The checked traffic covers seven frames and 32,825 writes, all six header fields,
the saturating header counter, a payload larger than 64 KiB, 24-bit address wrap,
ignored upper address and odd byte-address/count bits, and both serial data pins.
It also checks startup, CPU reset/release commands, the version reply/status word
and zero-filled out-of-range version reads. Valid version bits are compared with
the original; its undefined out-of-range output is intentionally excluded.

A separate directed check changes ECS alone while holding all memory selects
constant, exercising the corrected bank-mapper sensitivity list in every
configuration with 0.5 MB chip RAM.

## S4 live status-read ownership

Version/status reads must leave `bus_req` low throughout the header, payload
and completion delay. They use internal metadata, not SRAM. The regression
continues comparing write/reset ownership and all other physical bus signals
with the historical implementation, including the write drain delay.
`firmware/arm/tests/test_version_transport.py` additionally drives the real
MIA from the production ARM reader and checks that repeated clock reads do
not take the Amiga memory bus.
