# Datapath checks

Run `bash tests/datapath/run.sh`, `bash tests/datapath/compare_baseline.sh` and
`bash tests/datapath/check_dma_write_bus.sh` from the repository, or run the
complete `scripts/run_regressions.sh` suite. They need Icarus Verilog; the bitplane and whole-Blitter tests
also use ISE's unisim library (`ISE_UNISIMS` overrides its installation path).
The comparison extracts the original Blitter from commit
`a8c27a167cec5598fd439cbbef11ea1591d09c90`; `BASELINE_REV` can override it.

The tests cover:

- 11,036 CPU-write and DMA pointer transactions, including signed modulo,
  control-bit cancellation, wraparound, and the first-line-pixel D-pointer bypass.
- Every minterm truth table and input combination independently on all 16 lanes.
- All 1,024 ECS/OCS resolution, BPU and fetch-sequence combinations, including
  disabled planes 6/7 and the ignored AGA BPU3 bit.
- 256 complete rectangular/line blits compared cycle by cycle with the original
  implementation: 20,347 clock cycles and 3,565 DMA grants, including stalls,
  channel masks, shifts, fills, signed modulos and both OCS/ECS size registers.
- All four audio DMA pointers reloading and crossing the 2 MB address boundary,
  compared with the original connected output bits after removing unused bit 21.
- The dedicated DMA write bus through the actual top-level Floppy, Paula,
  Agnus and Gary wiring: 65,536 combinations, including 41,008 DMA writes whose
  data exactly matches the original complete custom-register readback bus.
  Coverage includes all 128 DMA-request combinations, disk direction, all
  Blitter channels and slowdown counts, CPU read/write requests and all 256
  CPU register addresses, each data-bit lane, first-line-pixel and host override.

The pointer change affects the address-generator output when no pointer update
is enabled. Agnus only consumes that address on granted Blitter DMA cycles.
The whole-Blitter test explicitly checks that every grant enables its pointer
and compares the resulting address, data, register address and strobes.

The dedicated DMA bus carries raw disk FIFO output through Paula to Agnus,
where highest-priority disk DMA selects it; otherwise the already grant-qualified
Blitter D word is selected. Gary uses this bus only for memory writes while DMA
owns the bus. CPU register readback, FIFO pop strobes, DMA arbitration, register
addresses and memory-cycle timing are unchanged. Its data is unspecified during
DMA reads, when SRAM is not written. The whole-core combinatorial test checks
the original and dedicated buses on every DMA write and checks CPU/host write
data and all SRAM strobes independently. It uses forced requests/held data to
enumerate arbitration combinations, while the separate complete-Blitter and
Floppy FIFO regressions cover their sequential operation.

## Isolated minterm synthesis

ISE 14.7 XST, XC3S400-4-PQ208, speed optimization level 1, no I/O buffers,
resource sharing and XOR collapse enabled:

| Implementation | LUTs | Slices | Estimated combinational delay |
| --- | ---: | ---: | ---: |
| Original sum of products | 80 | 41 | 2.670 ns |
| Truth-table lookup | 64 | 32 | 1.592 ns |

Reports are in `reports/datapath/minterm-before.syr` and `minterm-after.syr`.
These are isolated synthesis estimates; whole-core routed timing determines
whether the final build meets its constraints.
