# Minimig ARM setup firmware MM2609S5

Target: the AT91SAM7S256 ARM controller on the six-SRAM XC3S400 Minimig.
Release **setup-s5-20260917** pairs **MM2609S5** with FPGA
**PI FMG260917S550Mhz**. Download the exact
[S5 release pair](../../releases/setup-s5/README.txt); no rebuild was performed
for promotion. The S4 FPGA / S3 ARM rollback pair is included.
S5 adds an optional 60 MHz profile advertised by FPGA feature bit 4.
Four-profile cores keep their original choices; a saved 60 MHz setting
falls back to 50 MHz on those cores. The default stays 50 MHz.
See [the S5 implementation and timing notes](../../docs/setup-s5.txt).

The approved compact OSD, changed-row navigation, complete clock-status
readback and S4 metadata-read bus-ownership fix are retained.

The board baseline is [Minimig ARM_ASB230428_6MB](https://www.minimig.ca/source/minimig197itx/ARM_ASB230428_6MB.zip).
`IMPORT.json` records the original source hashes. `PORTS.json` records the
AmiCube storage reference and local adaptations. Board pin assignments,
48 MHz ARM setup, legacy IDE transport, F80000 ROM upload and the existing
124-byte MNMGCFG0 configuration layout are retained. This firmware is not an
AmiCube Spartan-6 board image.

## Use

The new OSD shows both firmware versions. In Settings → Chipset, select CPU
Turbo, choose 20/30/40/50/60 MHz, then choose **Apply clock & reset**. The star
marks a pending selection. Save Settings preserves the choice across power
cycles; old configuration files default to 50 MHz. Normal remains 7 MHz.
Applying a clock deliberately resets the Amiga. The FPGA version string
identifies the build/default clock; the clock menu shows the selected profile.

Hard Disk settings retain HDF files and add whole SD card, primary MBR
partitions 1–4, and partition HDFs with generated RDB metadata. Unsupported,
empty and out-of-card MBR extents are not offered. Raw modes write through
to the chosen card/partition. Choosing a mode does not format or repartition
the card. GPT and extended/logical MBR partitions are not implemented.

The S2 display uses AmiCube's native 8×8 font on a 64-column, 16-row panel
with a separate navigation column. VGA draws 512×128 output pixels (half S1's
panel height and half its character width/height). At 15 kHz, characters retain
eight real scanlines and use 14 MHz horizontal pixels for readability. The
panel centers on the PAL/NTSC raster. The original S1 palette is retained. The 24x24 PCB logo receives horizontal
aspect correction at 15 kHz, so its cross is not stretched vertically.
The cross logo comes from the Minimig-198itx PCB footprint
`Libs/Graphics/MinimigLogo01.kicad_mod`, retained in `assets/`.

The footer reads the FPGA's applied clock profile and Normal/Turbo mux state.
It displays an unconfirmed state if readback fails; the fixed version suffix
continues to describe the build's default. S1 and R7 FPGA fallback modes remain.
The ARM UPG header and OSD version both use `MINIMIG_ARM_VERSION`.

For like-for-like SysInfo results, preserve the owner's enabled command in
`S:User-Startup` that prioritizes cached slow RAM over uncached fast RAM.
Disabling fast RAM restored the expected readings on the owner's board;
clock ratios and cache timing were not changed in response.

Old FPGA images fall back to the legacy OSD and do not receive clock-profile
commands. New FPGA images retain the old OSD protocol for old ARM firmware.
Features are identified by an explicit MIA signature/ABI/mask, independent
of the displayed date or build label.

## Build and verification

```
make -C firmware/arm
bash firmware/arm/tests/run.sh
python3 firmware/arm/tests/audit_upg.py firmware/arm/firmware_rom.bin firmware/arm/FIRMWARE.UPG MM2609S5
python3 firmware/arm/tests/audit_samba_image.py firmware/arm/firmware_rom.bin
```

The makefile defaults to GNU Arm Embedded 10.3 at its installed path;
`GCC_PATH=/path/to/bin/` overrides it. The firmware and upgrade header share
`MINIMIG_ARM_VERSION` in `inc/setup.h`. `FIRMWARE.UPG` is the ordinary
512-byte MNMGUPG header plus the raw Flash image. `firmware_rom.bin` is the
raw SAM-BA image for Flash base 0x00100000. Building does not flash the ARM.

Host tests exercise the actual renderer, configuration load/save, raw HDD
backend and FAT mount code; unit tests cover MBR bounds, RDB, ATA progression
and CSD capacity. The ARM-produced cells are sent over simulated SPI into
the FPGA OSD and checked against an independent font expansion at both
15 kHz and VGA rates in PAL and NTSC. ARM ELF layout,
vector targets, UPG payload and both CRCs are checked separately.
The version-transport regression links the production ARM reader and status
decoder to real `Mia.v` via Verilator, including the final status word at
three SPI rates. The host suite requires Verilator and Icarus Verilog.

Source notices remain in each imported file. See `THIRD_PARTY.txt` and the
GPL text in `COPYING` for redistribution notices.
