# SRAM write timing review

## What the DMA change preserves

The dedicated write bus selects the floppy FIFO when disk DMA wins
arbitration, otherwise the Blitter's D-channel data. Disk DMA has the
highest priority and selects DSKDATR during memory writes. Blitter output
is already qualified by its grant and D-channel selection. The register
readback bus and the SRAM bridge's address, write, byte-enable and chip-enable
state machines retain their original behavior. MIA ownership still selects
the host CPU-data path through Gary.

The top-level regression checks 65,536 arbitration/address/data combinations,
including 41,008 DMA writes, against the original complete custom-register
readback expression. This establishes write-data selection equivalence at
settled RTL values; it does not establish the SRAM pin timing.

## Cycle end needs a board timing budget

The original SRAM bridge deasserted write enable, chip select, byte enables
and FPGA data drive in Q0. Chipset arbitration and data could change on that
same 7 MHz edge. Shortening a combinational write-data path reduced the
time for which the old word remained on the bus after Q0.

The revised bridge captures write data in 16 registers at Q2, on the same
edge that asserts write enable. It holds that word until a later Q2 write.
At Q0, nominally 70.484 ns after Q2, the write controls deassert while data
remains driven. A falling-edge copy of the output enable extends data drive
until Q0 plus 17.621 ns. The next read's output enable starts at Q1, another
17.621 ns later. No SRAM pin drive-strength or slew setting changed.

Q2 capture allows data to arrive after Q1. CPU byte-write enables at Q2 use
the CPU strobes sampled at the previous Q1 edge. The 68000 bus protocol
provides write data before asserting those strobes. DMA and MIA write words
are generated on the chipset clock and have Q0-to-Q2 settling time. The
33 ns TS20 budget checks CPU pads to the new write registers. The CPU's
actual timing at 60 MHz still needs hardware qualification.

The SRAM regression covers 1,563 transactions, all banks and byte enables,
late data between Q1 and Q2, Q0 source-data changes, and read/write
turnaround. Its SRAM model samples data 2 ns after the write-ending edge.
Removing the holding register, capturing at Q1, or removing the extended
drive causes that regression to fail.

For each SRAM byte and selected bank, determine the earliest terminating
write control recognized by that SRAM (write enable, chip select or byte
enable, according to its datasheet). Compare that event with the earliest
data change or FPGA output disable, including clock insertion differences,
output loading, PCB skew and the SRAM's specified data hold time. Also
check write pulse width, setup to write end and bus turnaround.

The maximum-delay constraints cannot alone prove these relationships.
A zero TRACE hold-error count
for the internal clock constraints is not an external SRAM hold check.

The SRAM's data setup/hold requirements apply at the signal ending the
write, which permits the Q2 register's output to settle after write enable
assertion. The actual installed part's specification remains authoritative.

## Earlier direct-bus experiment

The direct DMA bus alone preserved settled write values but left the
same-edge output hold race. In `dma-direct-opt1`, the minimum data-drive
release path was 9.462 ns while the maximum write-enable path was
10.571 ns. These were not complete pin hold margins; they motivated the
registered data and delayed-release change now included in the final build.

## Registered-write routed check for 5016887

`build/sram-hold-release-03/` holds a copy of the completed
`release-60mhz-03` route. Additional FROM/TO groups isolate the falling-edge
`doe_hold` register, write-data registers and RAM-to-write-register paths.
The final route passes this focused audit with zero timing errors and
zero warnings. Portable measurements and original report excerpts are in
`reports/implementation/sram-hold-summary.json` and
`reports/implementation/sram-hold-focused.txt`. The removed direct
RAM-to-pad constraint is absent; RAM-to-write-register coverage is explicit.

| FPGA path | Measured delay |
| --- | ---: |
| CPU data pad → Q2 write register, 16 paths | 13.221 ns maximum |
| RAM → Q2 write-register data/control, 1,072 paths | 21.015 ns maximum including uncertainty |
| Q2 write register → SRAM data pad | 11.150 ns maximum |
| Falling-edge output-enable register → data pad | 9.829 ns minimum / 12.256 ns maximum |
| Write-enable register → write-enable pad | 11.681 ns maximum |
| Read-output-enable register → output-enable pad | 10.329 ns minimum |

Combining these data-path bounds with the nominal half-cycle separation
gives 15.769 ns between latest write-enable termination and earliest data
release, and 15.694 ns between latest data release and earliest next read
output-enable assertion. These are **FPGA data-path-only separations**;
they exclude residual launch-clock differences, PCB skew and the actual
SRAM requirements. They must not be labeled guaranteed board hold or
turnaround margins.

## R2-04 routed check

The same Q2 holding register and delayed output-enable release are
preserved in R2. Its final route passes the focused external audit with
zero errors and zero warnings. Results and source hashes are recorded in
`reports/r2/external-timing-summary.json`, with original path excerpts in
`reports/r2/external-timing-focused.txt`.

| FPGA path | R2-04 measured delay |
| --- | ---: |
| CPU data pad to Q2 write register, 16 paths | 12.045 ns maximum |
| RAM to Q2 write-register data/control, 1,072 paths | 18.686 ns including timing uncertainty |
| Q2 write register to SRAM data pad | 10.257 ns maximum |
| Falling-edge output-enable register to data pad | 11.151 ns minimum / 14.272 ns maximum |
| Write-enable register to write-enable pad | 11.200 ns maximum |
| Read-output-enable register to output-enable pad | 10.388 ns minimum |

The nominal half-cycle plus these path bounds gives **17.572 ns** between
latest write-enable termination and earliest data release, and
**13.737 ns** between latest data release and earliest next read enable.
These remain data-path-only separations: residual clock differences,
jitter, PCB/loading and the installed SRAM's requirements are excluded.
They must not be described as guaranteed board hold or turnaround margins.

## Protocol references

- [NXP M68000 User's Manual](https://www.nxp.com/docs/en/reference-manual/MC68000UM.pdf),
  section 5.1.2: write data is driven in S3 before data strobes assert in S4.
  The manual's rated-frequency timing numbers do not establish operation
  at the core's 60.297 MHz turbo clock.
- [Infineon CY7C1061GN/CY7C10612GN data sheet](https://www.infineon.com/dgdl/Infineon-CY7C1061GN_CY7C10612GN_16-Mbit_1M_words_16_bit_Static_RAM-DataSheet-DataSheet-v01_00-EN.pdf?fileId=8ac78c8c7e7124d1017f1c7308e61654),
  page 9: representative asynchronous SRAM write-end setup/hold semantics.
  This reference does not identify the part installed on the user's board.

## Hardware information and useful tests

Obtain the SRAM part/speed grade, CPU part/speed grade and relevant board
timing or measurements. Exercise floppy DMA and Blitter-heavy software,
memory patterns that toggle every data bit, byte writes, and CPU/MIA bus
turnaround in both CPU speed modes. Cold-start and repeated-reset tests
are also needed for the revised DCM sequencing. Functional tests increase
confidence but do not replace a setup/hold budget across voltage and
temperature.
