# S5 release: implementation and timing

S5 adds **20/30/40/50/60 MHz** clock selection to the OSD and restructures
the CPU acknowledgement output to seek more timing margin. The default
remains **50 MHz**. Released as **setup-s5-20260917** at the owner's request,
using the exact SD-card pair without a rebuild. Hardware testing against the reported
intermittent 50 MHz instability remains a follow-up; its cause has not been
established. See [the release package](../releases/setup-s5/README.txt) and
[release/hardware record](setup-s5-hardware-results.txt).

Versions shown in the OSD:

- FPGA: **PI FMG260917S550Mhz**
- ARM: **MM2609S5**

## Changes

The 60 MHz profile runs at 60.2972184 MHz using the existing 120.5944368 MHz
divider. The 50 MHz profile remains 49.6565328 MHz and Normal remains
7.0937904 MHz. The chipset clocks, reset-time switching sequence, compact
centered OSD, Minimig cross logo, partition support and S4 navigation-flash
fix are retained. No additional DCM, BRAM or global clock buffer is needed.

The ARM offers 60 MHz only when the core advertises the new capability.
Existing cores keep their four choices. The 124-byte configuration layout
and previous indexes are preserved; a saved 60 MHz setting falls back to
50 MHz on a four-profile core. The clock footer reports the applied profile.
The FPGA version suffix identifies the build default, not the active speed.

The ACK output has separate precomputed read, write and cache guard terms.
Its truth table, cache eligibility rules and registered response sequence
are unchanged. Exhaustive equivalence checks cover all 256 input combinations,
and integration tests cover cached/uncached reads, writes and bus retirement.

## Timing and validation

Each sweep launches **four isolated ISE builds concurrently**, using distinct
MAP/PAR seeds and one committed source snapshot. Selection requires zero
errors in main, Normal and component timing, followed by independent external
bus, chipset phase, retirement, Blitter, read-capture and clock-selection
audits. Failed routes and their original reports are retained in the evidence
archive; they are not test images.

The final CPU PERIOD is **16.584513 ns**, covering the fastest profile, versus
20.138337 ns in S4. The ACK limit is **5.75 ns**, compared with the released
6 ns. Earlier 5.5 ns trials did not close and are recorded as failures.
Other active bus limits, jitter reserve and Normal-only classifications are
unchanged. The routed clock-select audit checks every profile, retaining
0.60 ns setup from [AMD/Xilinx DS099, Table 57](https://docs.amd.com/api/khub/documents/y7TWBeO97VdEfASgDFNn~Q/content)
and the existing 0.50 ns reserve, including both edge checks in the vendor SDF.

The selected route is batch **F, seed 8**, built from
`51d530327a51f017095f9ea13ca6752e26b5c625`. Six batches, each with four
concurrent builds, produced 24 routes. The first four qualified under the
original 6 ns ACK limit; the later selection uses the stricter limit and
restructured logic. Full per-route results are in
[the release timing comparison](../releases/setup-s5/timing-comparison.json).

| Timing measure | Released S4 | S5 F/8 |
| --- | ---: | ---: |
| Worst ACK output delay | 5.789 ns | 5.391 ns |
| ACK slack against each build's limit | +0.211 ns / 6 ns | +0.359 ns / 5.75 ns |
| CPU slack at each build's fastest profile | +2.619 ns / 50 MHz | +0.511 ns / 60 MHz |
| Chipset 28 MHz slack | +2.262 ns | +0.281 ns |
| Chipset 7 MHz slack | +2.001 ns | +2.783 ns |
| Read-return output slack | +1.839 ns | +1.393 ns |
| 120 MHz divider slack | +2.146 ns | +2.126 ns |

The ACK path is **0.398 ns faster**. Some other paths have less headroom;
this is not an across-the-board margin increase. Main, Normal and component
timing each have zero errors. Existing ISE warning types/counts match S4,
including 61 synthesis warnings; no warnings have been hidden or suppressed.
The minimum external ACK reference margin at 60 MHz is 1.079 ns, after the
existing 5 ns setup reference and 0.5 ns reserve. These are modelled FPGA
intervals, not a characterization of the overclocked CPU or PCB.

All seven independent route audits pass for F/8. The clock-mux check retains
3.072 ns minimum margin after its setup requirement and reserve.

The FPGA regression suite and additional CPU/SRAM/retirement tests at 60 MHz
pass. Clock tests cover all 25 ordered turbo-profile pairs, Normal transitions,
reset sequencing and reserved SPI commands. ARM build and host tests pass,
including capability detection, configuration compatibility, clock readback,
partition storage and PAL/NTSC rendering at 15 kHz and VGA. The ARM build has
no compiler warnings; upgrade CRCs, vectors and memory layout are verified.

The package includes exact source hashes, route reports, all sweep results,
validation logs and checksums. Electrical behaviour of an overclocked CPU and
board remains a hardware-test question; positive FPGA timing alone does not
prove the reported instability is fixed.

## Install and test

Use the paired **MINIMIG1.BIN** and **FIRMWARE.UPG**. Put them at the SD-card
root, load the new core, then use the existing ARM firmware-upgrade menu.
Confirm the FPGA and ARM versions above in the OSD after restarting.
`ARM_MM2609S5.bin` is the raw SAM-BA image, not the ordinary menu-upgrade file.

In Settings → Chipset, select Turbo and the desired clock, then choose
**Apply clock & reset**. Save Settings retains the selection. Test 50 MHz
first with the workload that was unstable, then try the optional 60 MHz mode.
Also check cold boots, Normal mode and OSD navigation with the same RAM
configuration. Preserve the enabled slow-RAM-priority command in User-Startup
for comparable SysInfo readings; uncached fast RAM affects that benchmark.

The package includes the exact released rollback pair: rename
**ROLLBACK-S4.BIN** to `MINIMIG1.BIN` and **ROLLBACK-S3.UPG** to `FIRMWARE.UPG`
and use the normal update procedure. No disk image or startup configuration
is changed by this package.
