# S4 FPGA status-read bus ownership

Released as **setup-s4-20260917** with ARM **MM2609S3** on September 17,
2026. After receiving this exact FPGA image, the owner reported "Fixed" and
requested release promotion of both binaries. The navigation-flash fix is
owner-confirmed; further testing is planned. See the
[hardware record](setup-s4-hardware-results.txt) and
[release package](../releases/setup-s4/README.txt).

The owner confirmed ARM S3 displays the clock correctly. They still saw brief
line flashes across the Amiga picture while navigating the OSD; the picture
was crisp and stable otherwise. S4 keeps the approved S2 display and ARM
**MM2609S3**, and identifies the FPGA as **PI FMG260917S450Mhz**.

Each menu-page redraw refreshes the clock footer through MIA. Although MIA's
read reply comes entirely from its internal version/status logic, it asserted
`bus_req` during reads and their completion delay. At the top level that signal
suppresses Agnus DMA requests, parks the CPU bridge and invalidates its cache.
Interrupting those live accesses is unnecessary for metadata reads and
explains a concrete mechanism for the reported flashes outside the OSD.

S4 asserts ownership only for SRAM writes and their existing drain delay.
Version/status reads retain the same SPI framing and busy handshake, with no
Amiga memory-bus takeover. ROM/SRAM upload behavior and write ownership are
checked against the historical MIA implementation. CPU, SRAM bridge, clock
generation, cache implementation, display layout and font RTL are unchanged.
This fixes an observed protocol defect; the owner subsequently confirmed the
fix after the S4 SD-card test.

The production ARM-reader/MIA regression reproduces a 300,580 ns bus takeover
with the old FPGA at the test's 1 MHz SPI rate. The fixed logic never requests
the Amiga bus across repeated status reads at 1, 10 and 15.625 MHz, for all
four Turbo profiles, Normal and not-ready states. The SPI regression separately
checks 32,825 writes per run, including continuous payloads and retained write
drain timing. Source identities and final route reports accompany the package.

The write-operation qualifier adds paths to the cached-word and selector CE
pins. In settled Normal mode the cache is disabled and those values cannot
reach the CPU. The existing Normal-only inactive-cache timing model therefore
classifies these exact operation-register-to-CE paths too, under strict source
proof and negative-control tests. It does not exclude operation paths to
AS/reset, active read receipt, or RAM pins; Turbo and the CDC inventory keep
the CE paths timed. No active timing budget or clock period is relaxed. The
initial reports and the final reviewed reports are retained separately.

The routed S4 design uses 3,355/3,584 slices (93.6%), 16/16 BRAMs and 6/8
global buffers. Main, Normal and DCM-component timing reports have zero
errors. The explicit ACK and read-return budgets retain 0.211 ns and 1.839 ns
reported slack, respectively; the 120 MHz divider is still covered. These
are tool checks; the owner-confirmed navigation result and the remaining
hardware-test scope are recorded separately.
External-bus, chipset-phase, CPU-retirement, Blitter-completion, read-capture
and clock-selection audits also pass, together with their guard tests. The
read ACK reference margin is 3.407 ns; clock-selection minimum margin is
5.499 ns after its setup allowance and reserve.

The owner also reported that a 7 MHz boot reached an empty Workbench desktop
without finishing; a second attempt booted successfully. Treat this as an
intermittent report. It has not been reproduced or attributed to a specific
cause. Normal-mode CPU/SRAM, cache eligibility, bus retirement and clock tests
are included in the regression suite. Their success is not a Workbench boot
test. Repeat cold boots with the same disk image at Normal 7 MHz after the status-read fix;
preserve its enabled slow-RAM priority command and current settings.

On the existing S3 ARM, replace only `MINIMIG1.BIN` on the card and power-cycle.
No ARM flash is required. `ROLLBACK-S2.BIN` restores the previous FPGA; the
matched S3 ARM upgrade is included only for cards that have not yet installed
it. Disk images, ROMs, startup commands and saved settings are preserved.
