# S3 ARM navigation and clock-status update

Owner follow-up: the clock now displays correctly. Brief lines still blink
across the Amiga picture during navigation. S4 fixes the FPGA status-read bus
takeover while retaining this ARM binary; see [setup-s4.txt](setup-s4.txt).

The owner tested S2 and described the OSD as looking very good, with slight
flickering while navigating. Preserve its layout, colours, font, centering
and Minimig cross. ARM **MM2609S3** uses the exact S2 FPGA binary
**PI FMG260917S250Mhz**; this follow-up does not require an FPGA recompile.

Every selection move in S2 redrew eight menu rows and nine frame/tab rows.
Those 17 live display-RAM transactions include identical text and styles.
S3 retains a 2 KiB shadow of the last transmitted character/style rows and
sends only changed rows. The same selection move now writes two rows,
reducing display payload from 2,193 to 258 SPI bytes (88.2%). A repeated
identical page writes no display rows. The new category is selected before
drawing the frame, avoiding an intermediate old tab on a page change.

This reduces a plausible source of the observed flicker; physical improvement
still needs the owner's test. Display updates remain live, with no claim of
frame-atomic redraws. The FPGA, CPU/cache, clocks and their routed timing are
unchanged. No disk image or startup command is modified.

The shadow is invalidated by `SetupIdentity`, including after FPGA core
reload. Normal clear operations update the shadow along with display RAM.
The live clock footer still refreshes on status changes and failed readback.
S1 bitmap and R7 legacy display paths retain their previous behavior.

The owner also reported `CPU clock: not confirmed` in the F12 menu. The ARM
requested 32 bytes but clocked 34 to account for MIA's two-byte reply pipeline.
MIA counts that initial empty word too, so its read state ended before the
last status word could be returned. S3 requests and clocks 34 bytes, retaining
the same 32-byte identity result. This repairs the readback without changing
the selected clock or trusting the saved setting in place of live status.

A new test links the production ARM reader and status decoder directly to
Verilated `Mia.v`. The S2 reader reproduces the missing final word (`00 00`);
S3 receives the full `43 xx` status for all four Turbo profiles, Normal and
not-ready states at three SPI rates. Repeated reads also finish and release
the MIA bus. The earlier HDL-only MIA test requested 40 bytes, which had
masked the ARM's shorter-request bug.

The navigation regression reproduces 17 row writes on S2 and two on S3. It
checks both changed highlights, unchanged surrounding content, identical
redraw suppression, enable/disable, one tab update per page change, live and
failed clock readback, scrolling, and full redraw after FPGA reload. The
ARM host suite and PAL/NTSC 15 kHz/VGA raster checks are rerun on S3 output;
UPG CRC/version, Flash vectors and RAM/ELF layout are audited separately.
The version transport test requires Verilator in addition to the existing
C compiler and Icarus Verilog tools.

On a card already running the S2 FPGA, install only the new `FIRMWARE.UPG`
through the OSD firmware menu and power-cycle. The expected versions are
ARM `MM2609S3` and FPGA `PI FMG260917S250Mhz`. The S2 ARM upgrade is retained
in the package as `ROLLBACK-S2.UPG`; rename/copy it to `FIRMWARE.UPG` to
reinstall the previous ARM if needed.
