# S2 compact setup display

Owner feedback on S1: the colours are good, but the OSD is too large and is
not centered. S2 uses the AmiCube 64-column, 16-row arrangement, the existing
8x8 font, a separate navigation column, aligned menu content, blue frame and
the 24x24 Minimig PCB cross and chip outline within the existing header.
ARM `MM2609S2`, FPGA `PI FMG260917S250Mhz`.

The panel is rendered at the final video raster. VGA uses 512x128 native
pixels, reducing S1's displayed font width and height by half and its panel
height by half. At 15 kHz, the same 512 pixels are clocked at 14 MHz and each
glyph retains eight actual scanlines for readability. Its horizontal margins
are 121 hires pixels on both sides of the visible raster; its vertical center
follows the measured PAL/NTSC frame length. The palette is unchanged. No bitmap downsampling is
used. The 24x24 PCB badge fits the existing three-band header; at 15 kHz its
horizontal pixels are repeated so the cross remains square on the display. The actual ARM glyphs and SPI cells are checked against all four raster
combinations, including the complete outside-window area.

A 1024-cell character/style RAM plus a shared font ROM avoids a large bitmap.
Together with the legacy bitmap these use three BRAMs. S1's bitmap used two.
S2 advertises feature bits 0 (clocks), 2 (compact OSD) and 3 (active clock
readback), retaining ABI 1. Commands 0x70–0x7F write 64 character/style pairs
per row; OSD enable bit 2 selects the compact display. An S1 ARM falls back to
the legacy OSD on this FPGA. The S2 ARM retains S1 bitmap and R7 legacy support.

MIA word 15 is `0x43xx`; the low byte contains the ready flag, settled Turbo
mux selection and active profile. The ARM refreshes this status after applying
a clock and when drawing a page. A failed read is displayed as unconfirmed;
it is never replaced by the requested value. The build-version suffix still
identifies the default clock, not the active profile. The FPGA label is now
derived from the top-level ratio name rather than a separate hardcoded 50.
The ARM upgrade header and displayed version share the same definition.

## Clock/performance feedback, September 17

The owner reported SysInfo figures of about 23 at the 30 MHz setting and 29
at 40 MHz, following about 39–40 at 50 MHz. They then disabled fast RAM and
confirmed performance returned to expectation, closing the clock/performance
concern. The source caches enabled slow-RAM ranges and Kickstart ROM, while
expansion fast RAM is uncached. Allocation in those different regions explains
why SysInfo readings must be compared with the same memory configuration.
The owner requested preferring slow RAM with their existing startup utility
and confirmed enabling the existing command in `S:User-Startup`. Preserve
that enabled startup file on future SD updates. The utility name has not been
inspected on the SD card; no assistant SD modification is claimed here.
The earlier Workbench icon/tool error was not independently reproduced.

All clock-generation ratios and the CPU/cache/bus logic are unchanged from S1.
The additional end-to-end SPI test verifies commands 0x98/99/9A/9B produce CPU
periods 49.754/33.169/24.877/20.138 ns with ISE's DCM and BUFGMUX models.
This is functional simulation, not a measurement of the physical board clock.
The user-confirmed memory finding is not a reason to alter DCM multipliers,
remove cache timing stages or relax the timing constraints.

The exact tested R7 60 MHz image and the previous S1 package remain available.
The owner tested S2 on September 17 and confirmed that the display looks very
good, including its layout and logo. They reported slight flickering while
moving through menus. The ARM-only S3 follow-up reduces redundant display
writes while retaining this exact FPGA image; see [setup-s3.txt](setup-s3.txt).
The owner also found the clock footer reported `not confirmed`. S3 corrects
the ARM request length so MIA's final clock-status word is returned; the
FPGA's clock generation and status encoding are unchanged.

## Implementation and verification

The final display source snapshot is `build/s2-compact-06`, ISE 14.7 with
timing-driven MAP cost 2. It occupies 3,390/3,584 slices (94.6%), 16/16 BRAMs,
4/4 DCMs and 6/8 global buffers. Main, Normal and DCM-component timing pass
with zero errors; the 120 MHz divider and opposite-edge paths remain covered.
No timing budgets or exceptions were relaxed. The CPU bridge, SRAM bridge
and profile-controller RTL are byte-identical to S1.

The final route also passes the external-bus, chipset-phase, CPU-retirement,
Blitter-completion, recorded-read-capture and clock-mux audits. The read ACK
reference margin is 3.208 ns; the minimum routed clock-selection margin is
5.032 ns after its setup allowance and engineering reserve. The capture
audit initially stopped at its pinned S1 `Clock.v` hash. Review confirmed
that S2 adds only the read-only status port and assignment; removing those
two lines reproduces S1 after newline normalization. The strict hash was
updated, and the capture, clock and negative-control guards all passed on
the same final route. Their timing budgets were unchanged.

The ARM image is 78,424 bytes, builds without compiler warnings, and passes
UPG CRC/version, vector/Flash and ELF/RAM layout checks. The new character
renderer passes 393,216 pixel checks through the real SPI receiver across
PAL/NTSC RGB/VGA. The separate margin check observes external raster stimulus:
121/121 pixels horizontally; 79/79 PAL RGB lines, 56/57 NTSC RGB lines,
222/222 PAL VGA lines and 177/177 NTSC VGA lines vertically. Both the 24x24
logo and its 15 kHz aspect correction are checked against the ARM's source
logo array. The font matches the AmiCube reference byte for byte.

The regression suite was resumed at two test harnesses after their explicit
source lists were extended for the new display modules. Earlier failed runner
logs remain in the evidence; all constituent test commands subsequently pass.
The independent margin test's stimulus counter offset was corrected before
the final run. No RTL change was made to accommodate that test discrepancy.

Remaining ISE warnings retain their reports: legacy unused/tied logic, a
trimmed high bit in the legacy OSD counter, XST's unpacked-slice estimate,
the existing SCK pin placement and intentional clock-to-data/pad routes,
and Amber's unused BRAM output. This invocation's PAR reported that it used
MAP cost 2 despite a redundant `-t 1`; the build helper now defaults PAR's
cost to MAP's cost to avoid that warning on future builds. This is not a
claim of zero warnings or of board-qualified timing/rendering.
