# S1 paired setup candidate

FPGA `PI FMG260916S150Mhz`, ARM `MM2609S1`. This branch adds OSD clock
selection, partition-backed disks and the AmiCube-style setup display with
the Minimig PCB cross. It is a test candidate, not a replacement for the
owner-qualified `r7-unified-20260916` 60 MHz release.

The earlier fixed 49.657 MHz image produced about 39 MHz in SysInfo and a
Workbench icon/tool loading error on the owner's 68SEC000. That image is
marked as failing hardware acceptance in `work/r7-50mhz-default-20260916`
(commit `39abb31`). The exact Workbench text and root cause are unknown.
Passing timing checks do not resolve that hardware observation. S1 needs
a new board test; its additional changes are not evidence of a cure.

## Clocks and bus behavior

| OSD label | Actual PAL clock | Source |
| --- | ---: | --- |
| Normal | 7.0937904 MHz | Original inverted chipset clock |
| 20 MHz | 20.0990728 MHz | 120.5944368 MHz / 6 |
| 30 MHz | 30.1486092 MHz | 120.5944368 MHz / 4 |
| 40 MHz | 40.1981456 MHz | 120.5944368 MHz / 3, balanced edges |
| 50 MHz (default) | 49.6565328 MHz | Original direct DCM, 14/2 |

The old compile-time label 52 corresponds to 53.203428 MHz (15/2); the
fixed 50 MHz candidate already used a direct DCM, not fabric division.

A profile command asserts reset, selects Normal, allows settling, changes
the unused Turbo source, allows settling, selects the requested mode and
holds reset for at least 128 CPU edges. The final mux selection is registered
on the selected CPU clock. Reset does not asynchronously alter that mux pin.
Legacy Normal/Turbo overlays preserve the selected profile. The chipset
clocks remain unchanged. See [UG331](https://docs.amd.com/api/khub/documents/divgj78jgBZqFZjIjXRfZA/content)
for the Spartan-3 clock-mux constraints; the route audit checks select setup,
including the additional edge checked by the vendor SDF.

The R7 recorded-read path is retained. Slower-profile tests exposed a write
admission hole: with late byte strobes, Q3 acknowledgment could occur without
a preceding Q2 SRAM capture. S1 admits Turbo writes only after the existing
28 MHz sampler has seen a byte strobe. An unready slot stays entirely idle,
including the custom-register Q0 write. A mutation removing the guard
reproduces the 20 MHz failure. This may add a chipset-slot wait to a late
write; it does not change the cache-hit or recorded-read pipelines.

## Protocol and saved settings

MIA words 11/12/13 contain signature `MS`, ABI 1 and feature bits 0 (clocks)
and 1 (extended OSD). Word 14's original Turbo-disable status is unchanged.
The ARM uses those fields, not version-string comparisons. OSD commands
0x98–0x9B request 20/30/40/50 MHz and reset. Commands 0x60–0x6F write sixteen
256-byte bitmap bands. Enable bit 3 selects the extended frame. Legacy OSD
commands and its eight bands remain available.

The former unused configuration version word stores 0x53430100 plus the
clock index 0–3. Unknown values select 50 MHz. The disk layout remains exactly
124 bytes. Clock edits are staged; Apply resets; Save Settings persists them.

## Verification and remaining limits

Production build: `build/s1-integrated-04`, ISE 14.7, XC3S400-4-PQ208.
Timing-driven MAP is required for this footprint. The final packed design
uses 3,377/3,584 slices, 15/16 BRAMs, 4/4 DCMs and 6/8 global buffers.
Main, Normal and DCM-component checks report zero timing errors. The derived
120 MHz constraint is required to cover the divider and opposite-edge paths;
50 MHz is the worst-case independent CPU PERIOD, with a separate related
Normal-mode check. No timing budgets are relaxed for the new features.

The full regressions pass. All four actual clock ratios and profile changes
are exercised with vendor primitive models. CPU-return, SRAM/DMA and actual
custom-register write tests run at every supported Turbo period. Mux tests
include all sixteen ordered profile pairs, interrupted resets, legacy mode
changes, route-delay stress and a rejecting select-setup control. The route
has separate external-bus, chipset-phase, retirement, Blitter, captured-read
and clock-mux audits. Final results and source identities accompany the
candidate package.

Remaining ISE warnings are retained in the reports: estimated unpacked slice
use exceeds capacity in XST, while timing-driven MAP fits; unused/tied legacy
logic; clock nets deliberately feeding the phase sampler/clock inverter and
forwarded output pad; the board's non-clock SCK pin P90; and an unused Amber
BRAM output bit. The clock-data routes receive explicit audits. The pin
assignment is inherited board wiring, not a newly suppressed warning. This
is not a claim of zero warnings or of hardware stability.

Host ARM tests cover real code and synthetic sectors. No card was formatted
or repartitioned, and the ARM has not been flashed. Hardware confirmation of
boot, SysInfo, Workbench, disk reads/writes and both video modes remains with
the owner. Keep the exact tested 60 MHz R7 image for comparison and rollback.

The final captured-read audit passes; its ACK setup reference margin is
3.212 ns. The routed profile-mux minimum margin is 6.027 ns after the
0.60 ns setup requirement and an additional 0.50 ns reserve. The Blitter
completion audit reports 7.333 ns minimum setup and 1.269 ns minimum hold.
The ARM clean build has no compiler warnings; the raw image is 75,952 bytes,
and the ELF RAM sections/stacks end at 0x002063d8 within the 64 KiB SRAM.

## Follow-up — September 17, 2026

The owner traced the low SysInfo readings to allocation in uncached fast RAM.
Disabling fast RAM restored the expected performance; they closed the clock
concern. Slow RAM and ROM are cached by this core. Keep comparisons in the
same memory configuration. This updates the performance diagnosis above;
it does not independently resolve the earlier Workbench message. See
[the S2 hardware-feedback note](setup-s2.txt#clockperformance-feedback-september-17).
