# R7: recorded CPU read responses

**Released on 2026-09-16 after the owner's successful retest.**
The exact R7 image is now the [unified TF030/68000 release](../releases/r7-unified/README.txt).
Earlier reports establish TF534 NORMAL/TURBO operation and 68SEC000 boot.
The latest retest confirms the restored image works; detailed configuration
and replacement storage benchmarks were not supplied. R3 remains the owner's
[preferred standalone SEC000 image](preferred-60mhz.txt).

The development history below describes the original implementation. R5 boots the SEC000 at
60 MHz but crashes starting Alien Breed; that game loads in Normal mode.
Both original-configuration TF534 and TF536 cards fail to boot R5 in Normal.
R7 addresses the shared CPU read-response sequence. On 2026-09-15, the user
reported that TF534 boots in Normal with R7 and that 68SEC000 also boots
(clock mode not yet specified), followed by TF534 Turbo operation. TF536 coverage and the SEC000
game regression still need testing. See [hardware results](r7-hardware-results.txt).

**Historical storage observation:** SysInfo storage speed on the same TF534 was reported at
about **5 KB/s in Turbo** and **364 KB/s in Normal**, against the user's expected roughly 2,000 KB/s.
The owner subsequently suspected the CF card and confirmed that the restored
R7 works. No new numeric benchmark or confirmed root cause accompanied that
retest; see the dated [hardware record](r7-hardware-results.txt).

Version: **PI FMG260915R760Mhz**. Normal remains **7.0937904 MHz** and Turbo
remains **60.2972184 MHz**. This release does not need an ARM firmware update.

## Reference and implementation

The reference is the latest
[AmiCube H20 source](https://gitlab.minimig.ca/ranko/AmiCube_V11_Codex/-/tree/0ef2e8f1ed240b5ec13b0dc8e30b88aab959d790/fpga/hard_floppy_virtual_ready_h20/hard/source),
commit `0ef2e8f1ed240b5ec13b0dc8e30b88aab959d790`. Ranko reports TF030 operation
at both selected 50 and 60 MHz on AmiCube. Its shared socket bridge is the
adaptation reference. The separate `cores/HARD/source` directory is historical;
the selected H20 generated directory happens to retain `build/r15h/xst_compat`
in its name.

The original Minimig uses asynchronous SRAM and a Spartan-3, so the response
sequence is implemented at its existing memory phases:

1. Capture fresh address-strobe ownership before admitting a read.
2. Record the returned word at the real chipset Q0 read-completion edge.
3. Synchronize completion into the CPU clock and fill the read cache directly
   from that held word while the CPU still holds its request.
4. Acknowledge on the CPU rising edge after the falling-edge cache commit.
5. Retain the word through address-strobe release while physical output enable
   turns off. R5's held cache-source selection is retained.

Internal acknowledgment remains separate because it schedules the original
Normal-mode service slot. CPU reset, clock readiness and ARM ownership present
idle address strobe to the bridge. Cache invalidation retains its own meaning.

Two abort faults were reproduced and corrected during prototype development:
asynchronous completion clearing could reopen read capture at cycle release,
and canceling a read between SRAM phases could make the old write-enable logic
infer a write. A synchronous service receipt prevents repeat capture. SRAM
write enable now requires an active write byte strobe.

The external write acknowledgment uses only the two bus acknowledgment
registers. Cache hits already require a read request, so including their
condition in the write arm was redundant. Removing it preserves the Boolean
result. The final expression factors cached acknowledgment outside the response
multiplexer to shorten its physical path. Internal feedback is unchanged.

The sticky read-fill receipt sets directly from synchronized completion and
retains its asynchronous address-strobe reset. Its set enable does not duplicate
the abort condition. The separate cache-fill pulse remains abort-qualified.
This removes a reset-mask timing path into an active clock enable without
changing the receipt's next state or acknowledgment latency.

## Latency and scope

The conservative response pipeline adds four CPU wait clocks to Normal
uncached reads in the paired timing fixture, approximately 564 ns. In Turbo,
internal-to-external acknowledgment gains about 50–66 ns; the number of extra
CPU waits depends on alignment with the chipset slot. Existing cache-hit lookup
latency is retained. These are measured model results, not an application
benchmark.

One CPU image remains the objective for SEC000/68000, TF030 and PiStorm.
There is no CPU-type selector. TF534 Normal/Turbo operation is user-reported;
TF536 coverage still needs confirmation.
The selectable 20/30/40/50/60 MHz prototype remains
separate, and the Toki investigation remains closed at the user's request.

## Validation status

The private prototype passed held-read, cache, CPU/SRAM, CIA read-to-clear,
DMA contention, independent data/output-enable delays, abort/retry and realistic
bus-owner handover tests. Tests preserve the failing earlier variants as
controls. The integrated R7 source passes full-core ISE UNISIM elaboration,
137 CPU/SRAM cases with 39,456 transfers, and 24 PiStorm cases with 3,072 reads.
The unchanged R4 PiStorm control still reproduces 64 bad release captures.
The existing peripheral, datapath, blitter, graphics, sprite, MIA and clock
groups pass. Quadrature mouse testing passes 1,692 steps and 1,840 checks.
The final receipt source also passes 36 bus-retirement cases with 14,624
transfers, 44 focused read-return cases, four specific failing mutations, all
32 top-level ownership/reset-mask combinations, cache invalidation and alias
checks, and 12,800 cache-bus accesses. Its results match the preceding equivalent
ACK expressions after normalizing snapshot paths. Two deliberately short
bus-owner diagnostics retain their documented limitation.

Functional evidence is retained in [reports/r7](../reports/r7/functional-inputs.json).
The common peripheral/graphics groups ran before the equivalent ACK rewrites;
the CPU/output/cache/SRAM/top-level groups ran again on the final receipt source.
The routed checks below are separate from those functional simulations.

Simplified cache and PiStorm test backends previously changed data in the same
simulation step as Q0, before the derived capture edge. Their updated models
explicitly retain the completed word for 1 ns after Q0. Actual SRAM/Gary and CIA
tests use their own models. This fixture assumption is separate from the
required physical setup/hold analysis.

The held-AS TAS diagnostic has the same Turbo write failure in R4, R5 and the
prototype; it does not distinguish the R5 game regression. Arbitrary short
bus-owner pulses and complete adapter/board electrical behavior are outside
the directed model coverage.

## Implementation status

The selected route is `build/r7-recorded-return-06-qualified`, with the same
physical circuit and source as `build/r7-recorded-return-06`. Main, Normal and
clock-component timing reports have zero errors. Its updated, reviewed Normal
model is described below; the original failed Normal report remains preserved.

Mapping uses 3,564 of 3,584 slices, 5,374 LUTs excluding route-throughs, and
3,788 registers.
BRAM/DCM/global-buffer usage remains 14/3/5. The unused original input latches
are trimmed. XST still reports 53 warnings: its old latch warning becomes an
unused-signal warning; the other warning messages are unchanged. This is not a
warning-free build.

Timing budgets retain their existing values. New held-read paths have separate
16 ns output and cache-input constraints, and the new read acknowledgment is
covered by the existing 6 ns acknowledgment constraint. The SRAM output-enable
register uses the known R4 placement. The existing write-ACK register is placed
near its output logic. External and read-capture audits pass on the same routed
NCD. These estimates do not establish TF534/TF536 boot compatibility.

The initial source missed the unchanged 6 ns acknowledgment budget by 0.207 ns
with PAR seed 1 and 0.214 ns with seed 2. All other main constraints passed.
Those builds produced no test bitstream. Factoring the ACK improved the cached
path; placing the existing write-ACK register near its output then closed the
main constraints. Normal analysis exposed the redundant active receipt-enable
path, prompting the sticky-receipt cleanup above. The selected route includes that
cleanup; no numerical timing budget is relaxed.

Normal analysis also has narrowly source-checked cache exceptions:
six reset/readiness/host source FFs to the 16 cached-word CEs and the source-selector
CE, plus two reset source FFs to the three cache RAM write-enable pins. These
target specific pins, not whole destination registers. Cached words can still update in Normal, but their
values are unobservable after the selector clears; cache hits require Turbo.
Mode changes require idle address strobe, reset/host ownership masks the bridge,
a Normal read waits through the recorded-response pipeline, and a subsequent
Turbo hit requires cache scrub and fresh classification. Normal keeps
`cache_active=0`: tag writes are disabled and the byte RAM clear writes use zero
data at address zero. All active receipt
paths, other Normal paths, and all Turbo paths remain timed. The source guards
also check the MIA ownership decode and its delay sequence.

## Routed margins and limits

| Check | R7 margin |
| --- | ---: |
| CPU at 60.297 MHz | +1.002 ns |
| Chipset at 28 MHz / 7 MHz | +1.221 / +2.296 ns |
| Held cached word / recorded word to CPU | +4.190 / +2.696 ns |
| ACK output constraint, worst path | +0.016 ns |
| Q0 capture hold, including reserve | +1.185 ns |
| Held word before earliest cache fill | +17.921 ns |
| Latest cache commit before earliest ACK at pin | +11.743 ns |
| Held read data before ACK at pin | +23.165 ns |

External ACK margins after the 5 ns SEC000 rated-speed setup reference and
0.5 ns allowance are +1.396 ns for writes, +1.325 ns for recorded reads, and
+0.520 ns for cache hits. The cache figure is 0.277 ns lower than R4's +0.797 ns;
this change improves response ownership and hold behavior, not every physical
path margin. Selector withdrawal takes 5.984 ns against its 6 ns limit.

The earliest CPU write-release bound remains +12.527 ns after custom Q0, or
+9.527 ns when crediting zero AS-pin delay. The Blitter completion audit covers
156,942 paths and 13 pins across four FFs, with minimum setup/hold margins of
+6.726/+1.308 ns. Phase-sampler setup/hold margins are +12.150/+18.380 ns.

The SRAM capture audit covers all 16 returned bits, nine read-control outputs
and 19 address outputs. Its smallest external control/access allowance is
82.389 ns; this is a budget for SRAM and board delay, not an identified SRAM
part's rating. Earliest read-control withdrawal leaves at least 12.241 ns of
capture hold with zero external delay. AS distribution, recovery and pulse-width
requirements are inventoried; arbitrary adapter waveforms, board skew and
overclocked CPU limits are not proven by the FPGA reports.

## Image identity

RTL SHA-256: `5b77dba9adfde7416e15dd53ef11c91bc5b0b5cf1949e718e61151af7e947a68`.

BIN SHA-256: `9a522b53ceba70566123a1886a08010fbecf0c2a042faa37727f3436fa7df67d`.

BIT SHA-256: `21e3fac607f12ac4353bb7d379db84555a5ddbf44aabfabfbab28149cda0edfb`.

NCD SHA-256: `9a8ab6ef211a6c5301f9ccc924f140e91764095f5223bf10bd757b9b228d7746`.

## Hardware test order

1. Fresh SEC000 Normal boot, then Alien Breed.
2. Fresh SEC000 Turbo boot, then Alien Breed and memory tests.
3. TF534 and TF536 separately: fresh Normal boot, then Turbo if Normal works.
4. Record the displayed version and whether the OSD remains responsive on a
   failed boot.

The preferred standalone R3 image and historical R4 image remain available
for comparison and recovery.
