# R7 recorded-read capture timing

The selected route passes the new capture audit and the existing main, Normal, component, external, phase, Blitter-completion and retirement audits. Subsequent [hardware results](r7-hardware-results.txt) include a user-confirmed TF534 Normal boot; broader qualification is pending.

* Source: `5b77dba9adfde7416e15dd53ef11c91bc5b0b5cf1949e718e61151af7e947a68`.
* Routed NCD: `9a8ab6ef211a6c5301f9ccc924f140e91764095f5223bf10bd757b9b228d7746`.
* Build: `build/r7-recorded-return-06-qualified`; detailed capture evidence: `build/r7-capture-audit-06`.

## Measured lower bounds

| Check | Margin |
|---|---:|
| 16 return FFs, related-clock setup / hold | 3.688 / 1.034 ns |
| Same-Q0 retiring-control hold, with 0.5 ns reserve | 1.185 ns |
| CPU byte strobes to SRAM WE, setup / hold | 24.069 / 7.088 ns |
| Held word before earliest cache fill | 17.921 ns |
| Latest cache fill before earliest ACK at FPGA pin | 11.743 ns |
| Held CPU word before earliest read ACK at FPGA pin | 23.165 ns |
| Receipt-to-ACK half-cycle setup / hold | 5.006 / 9.303 ns |
| Read ACK against forwarded-clock reference | 1.325 ns |
| SRAM control withdrawal versus Q0 capture, zero external delay | 12.241 ns |

The capture PERIOD partition checks all 16 return FFs and 80 physical endpoint pins; service-state coverage includes both FFs and three pins. Explicit inventories cover every returned word bit, both cache data ports, all nine SRAM read controls, all 19 address outputs, both CPU write-byte sources and each completion/receipt/ACK stage.

The first completion synchronizer capture receives zero positive latency credit. Cache fill follows at least 1.5 nominal CPU periods and read ACK at least two periods later. The calculations retain actual local clock insertion, data-path extrema and 0.5 ns engineering reserve. The separate latest-fill-before-ACK calculation uses the actual falling-edge BRAM clocks. Same-edge synchronizer hold uses intrinsic hold plus independent clock insertion extrema; common-edge clock jitter cancels, so it receives no additional arbitrary minimum-delay reserve.

The FPGA paths leave 85.091 ns for external OE access, 82.389 ns for the slowest control access and 82.769 ns for address access between Q1 and closing Q0. These are available budgets, not SRAM ratings; PCB delay and the actual SRAM specification must fit them. The related CLK0/CLKDV calculation uses the existing conservative 1.390 ns allowance. TRACE effective hold already includes the destination hold requirement and is not subtracted twice.

## Precise Normal exceptions

Only settled Normal mode receives these source-proven exceptions:

* `CLOCK1/clocks_ready_pipe_2`, `CONTROL1/rst_cnt_2`, `MIA1/rst_out`, and `MIA1/state_0/1/2` to the CE pins of `CPU1/cache_data_selected` and all 16 `cache_data_held` FFs.
* `CONTROL1/rst_cnt_2` and `MIA1/rst_out` to WEA on the three CPU cache RAM write ports.

The cached-word FFs can load in Normal; their values are unobservable because selection clears to zero and cache eligibility/ACK are disabled. Normal invalidation holds cache-active low, disables tag writes, and makes data-RAM writes the constant zero/address-zero clear operation. Turbo re-entry performs a full scrub and fresh lookup before a hit ACK. Exact source guards check those assignments, single writers, AS-high mode changes and the MIA ownership decode and ten-cycle bus-delay hold. All other Normal paths, every Turbo path, data/address pins, asynchronous reset pins and the active return/synchronizer/receipt/ACK pipeline remain timed.

The original failing route06 Normal reports are preserved. `normal-qualification-copy.json` records the unchanged source, UCF, NCD and main report in the qualified copy. This was a timing-model correction for inactive cache paths; the active receipt enable was separately simplified in RTL and remains timed.

## External limits and evidence

AS pad-to-reset timing is inventoried for all relevant consumers, including primitive recovery and reset-pulse requirements. For example, `read_as_seen` reset receives AS in 5.836–7.298 ns; its maximum recovery requirement is 0.883 ns and minimum reset width 0.863 ns at the primitive. The audit does not claim an external AS phase/pulse guarantee for an unknown CPU or adapter. The ACK calculation uses the existing 5 ns SEC000 rated-speed reference plus 0.5 ns reserve; it is not a 60 MHz CPU guarantee. Bundle bounds use nominal periods and stated engineering reserves, not an independently characterized CLKFX jitter measurement.

Portable evidence is in `reports/r7/read-capture-*`; the self-contained helper and frozen input manifest are in `scripts/read_capture_audit`. Seven capture guard cases (qualified baseline plus six rejecting mutations) and 13 Normal-model cases (baseline plus 12 mutations) pass. Full TRACE/SDF/netlist artifacts stay in the audit directory and release package.
