# R7 unified, nominal 50 MHz default

Requested September 16, 2026 after the owner approved the unified R7 release.
The existing 49.6565328 MHz profile replaces 60.2972184 MHz as the source
default. NORMAL remains 7.0937904 MHz. This candidate has an adverse hardware result and is not promoted.
The tested 60 MHz R7 remains the stable release.

The only production changes from `r7-unified-20260916` are the top-level
clock selection/date, standalone clock-generator default, and CPU PERIOD
constraint (20.138337 ns). The R7 CPU bridge and all other bus logic are
unchanged. OSD/MIA version: `PI FMG260916R749Mhz`. No ARM update is required.

Build `build/r7-50mhz-01` passes synthesis, MAP, PAR, main/NORMAL/component
timing and BitGen. External, chipset-phase, CPU-retirement, Blitter completion
and recorded-read capture audits pass. The Blitter audit needed 100 reported
paths per endpoint to expose all required hold subsets; budgets are unchanged.
NETGEN wrapped a BRAM port comma onto its own line; the timing-netlist parser
now accepts that whitespace without changing the required clock topology.

The complete regression suite passes. CPU-return, SRAM integration and
retirement positive cases use the actual 49.657 MHz period. Historical and
mutation controls retain their original 60 MHz period; other unchanged cache
and Blitter stress fixtures also remain at their original frequency.

Evidence: [reports/r7-50mhz](../reports/r7-50mhz). Preserve the exact tested
[60 MHz R7 release](../releases/r7-unified/README.txt) for rollback.

## Owner hardware result — September 16, 2026

The owner tested the 68SEC000 in 50 MHz mode and reported approximately
39 MHz in SysInfo, where their prior experience suggests approximately
48 MHz, plus a Workbench error involving loading an icon/tool (exact text
not captured). They consider the tested 60 MHz R7 more stable and faster
per MHz. Treat this image as failing hardware acceptance despite the
passing simulation and routed timing checks. The cause remains unresolved.

This image uses the original direct DCM CLKFX path with multiplier/divider
14/2 (49.6565328 MHz); it does not contain the selectable-clock prototype's
fabric dividers. The existing source label `52` means 15/2, which is actually
53.203428 MHz with this board's PAL reference. A ratio/phase comparison may
help diagnosis, but neither that ratio nor a new route is hardware-qualified.

## Follow-up — September 17, 2026

The owner traced the low SysInfo readings to allocation in uncached fast RAM.
Disabling fast RAM restored the expected performance; they closed the clock
concern. Slow RAM and ROM are cached by this core. Keep comparisons in the
same memory configuration. This updates the performance diagnosis above;
it does not independently resolve the earlier Workbench message. See
[the S2 hardware-feedback note](setup-s2.txt#clockperformance-feedback-september-17).
