# R5 candidate: hold cached CPU read responses through release

R5 fixes a reproduced cached-read release fault in the PiStorm CPLD/latch
model. It is built and passes the final regression suite and routed audits.
**Initial hardware testing found a regression.** With the 68SEC000, R5 boots
at 60 MHz but crashes when starting Alien Breed. The user had previously
reported that game stable on R4. The user then confirmed Alien Breed loads
in Normal mode. Both TF534 and TF536 cards in their original configuration
fail to boot R5 in Normal mode.
The Turbo regression and accelerator boot failure remain under investigation.
R4 remains the published, user-tested image.

Version: **PI FMG260915R560Mhz**. Turbo remains **60.2972184 MHz**.
Selected local build: `build/r5-cache-release-02`.
Source commit: `105ec82`; [retained evidence](../reports/r5/README.txt).

## Change and scope

R4 selected its cached word with combinational signals that cleared when AS
rose. Physical data and output-enable paths have different delays: switching
to the idle internal word before the FPGA stops driving can corrupt the
PiStorm external latch at cycle end, despite a correct earlier CPU sample.

R5 registers that selection at the existing cache-classification edge and
retains it through AS release. A fresh active request clears or reclassifies
the selection. Bypass withdrawal and restoration within the same transfer
also preserve data-before-acknowledgment ordering. The usual cache-hit
latency, held-word stage and CPU write acknowledgment are unchanged.

This is a shared socket-interface change, with no CPU-type selector. It
does not establish TF030 boot compatibility. Noncached read-return work and
20/30/40/50/60 MHz selection remain separate investigations; see
[development status](r5-unified-cpu.txt). The Toki investigation remains closed.

## Verification

The [maintained compatibility test](../tests/cpu-compat/README.txt) uses the
unmodified, licensed PiStorm CPLD source plus its external latch model:

- 24 cases / 3,072 candidate reads pass both pre-release and final-latch checks.
- Exact R4 controls reproduce 64 bad cached releases while every earlier
  sample remains correct.
- 105 source-transition and 75 bypass-restoration accesses pass. Three
  incorrect selector/ACK variants fail for their intended reasons.
- A synthetic 1 ns AS-gap refill failure remains in both R4 and R5. This
  separate limitation is recorded explicitly, without attributing it to
  a fitted TF030 or PiStorm card.

The final full regression suite also passes CPU/SRAM (137 cases / 39,456
transfers), bus retirement, cache aliasing, Blitter/CPU contention, graphics
and sprites, peripherals, mouse, host SPI, clocks and full-core elaboration.
The expanded timing-audit helper passes its focused guards and rechecks
historical R4 evidence successfully.

These are digital models and routed estimates, not a complete Amiga software
or board-level electrical qualification.

## Routed results

ISE 14.7, XC3S400-4-PQ208, area MAP at 95%, PAR seed 1. Main, Normal, DCM
component and external reports have zero timing errors. Timing budgets are
retained. The new selector is included in the existing 16 ns CPU-data,
20 ns byte-strobe and 6 ns acknowledgment path budgets. Source-checked
Normal-mode exceptions cover only inactive configuration inputs.

| Resource | R4 | R5 |
| --- | ---: | ---: |
| Occupied slices / 3,584 | 3,550 | 3,554 |
| LUTs excluding route-throughs | 5,360 | 5,368 |
| Slice registers, including latches | 3,780 | 3,781 |
| XST warnings, none filtered | 53 | 53 |
| BRAM / DCM / global buffers | 14 / 3 / 5 | 14 / 3 / 5 |

| Routed check | R4 slack | R5 slack |
| --- | ---: | ---: |
| 60.297 MHz CPU | +4.526 ns | +3.315 ns |
| 28 MHz chipset | +4.413 ns | +1.423 ns |
| 7 MHz chipset | +4.627 ns | +4.806 ns |
| Held cache word/selector to CPU data | +2.143 ns | +2.790 ns |
| Acknowledgment to CPU pin | +0.130 ns | +0.771 ns |
| Byte strobes to lookup/selector | +12.434 ns | +11.327 ns |

The routed acknowledgment estimates leave +1.117 ns for bus ACK and
+1.899 ns for cached ACK after the same 5 ns rated-speed setup reference and
0.5 ns engineering allowance. Held data leaves +17.985 ns. The selector's
5.229 ns acknowledgment-withdrawal path is checked separately under the
same 6 ns constraint; assertion still comes from the registered ACK.

Phase-sampler setup/hold margins are +11.828/+18.923 ns and interstage
margins +12.113/+19.482 ns after the documented clock allowances. The
nominal earliest CPU write release remains 12.411 ns after custom Q0, or
9.411 ns with zero modeled AS-pin delay.

All 111,130 paths into the four Blitter-completion/interrupt destinations
pass, across 13 physical pins. Minimum setup/hold slack is +9.521/+0.979 ns.
The initial report omitted a required related-clock hold example from its
20 shortest paths. Increasing report depth to 100 exposes the required
paths with identical timing constraints; minimum reported clk28-through-done
hold slack is +6.453 ns. No constraint or pass condition was relaxed.

## Candidate identity

BIN SHA-256:

```text
f5f4944c04b4ee4a14481daa2fe0bf0716ab2cfb7eb31a9c826005ffccde316c
```

BIT SHA-256:

```text
20326c48e873482f02cb84bcc2122dc3583a4bec989eb00531410171dea63b25
```

Routed NCD SHA-256:

```text
ca46dfc85da28499cb88a3266f62d83c21921b9b0540dd244f31ed7c2feb6393
```

A local review/test package is prepared in `build/r5-test-package`, including
`MINIMIG1.BIN`, the matching BIT, source/report ZIP and checksums. All package
checksums and all 25 archived build inputs were verified. Packaging did not
rebuild or change the image.

The candidate was copied to the SD card as `MINIMIG1.BIN` on September 15,
2026 at 14:27 EDT at the user's request. The previous R4 image was backed up
as `MINIMIG1-before-R5-20260915-142745.BIN.bak`; read-back SHA-256 matched
and `/dev/mmcblk0p1` was unmounted. The local receipt is `build/r5-sd-copy.json`.
The first 68SEC000 Turbo test reported the Alien Breed crash above. R5 has
not been published and is not approved as a replacement for stable R4. The first
`r5-cache-release-01` build lacks the bypass-restoration repair and is not
the selected candidate.
