# R4: Blitter final-write completion

**2026-09-16 preference update:** the owner now prefers the
[original R3 60 MHz image](preferred-60mhz.txt), reporting that ArmourGeddon
does not crash in the latest R3 test. R4 is retained for comparison. This
does not identify the cause or exact later build associated with the crash;
the earlier R4 observations below remain historical evidence.

**Publication follow-up:** the user reports solid 60 MHz operation on their
SEC000 board, with Alien Breed and additional games tested so far looking
clean, and has
authorized publication of this R4 binary and source. Hardware memory testing
and further game testing are pending. This is the exact tested image; no RTL
change or rebuild was made for publication.

After loading R4, the user reports that Toki still
rapidly strobes when the character/sprite enters the lower screen area in
turbo. R4 has not resolved this symptom. After further games showed no similar
issue, the user closed the Toki investigation for now. Its cause remains
unconfirmed, with software timing at turbo speed a plausible explanation.
R3 remains the pre-experiment reference. See the [updated investigation](toki-turbo.txt).
The release package and bitstream remain unchanged; the results below record
the implementation prepared before this follow-up.

R3 removed the user's Workbench corruption. WHDLoad Toki appears stable,
but the character's feet flicker continuously in a pit at turbo speed;
NORMAL is clean. `CUSTOM3=1` did not change that symptom. R4 addresses a
reproduced Blitter reuse hazard under DMA contention. A board test is still
needed to establish whether it explains Toki's flicker.

## Change

An area blit's final destination word remains in a pipeline after the
inherited busy flag clears. If higher-priority DMA holds that last write,
CPU starvation relief can admit a new destination-pointer write first.
The pending word then lands at the next job's address.

R4 completes destination-writing area blits when DMA grants their final
write. The same event clears busy/start, initializes B-shifter history and
requests the completion interrupt. This prevents a restart while a final
word is pending. Line and no-destination completion points are unchanged,
including line slots without a physical write.

This is a deliberate completion-timing policy change in both NORMAL and
turbo. Early busy clear is documented OCS/ECS behavior. It affects software
polling, Copper busy-dependent WAIT/SKIP and the Blitter interrupt; software
depending on that early timing may behave differently. Reprogramming
BLTCON0 during the final pipeline stages can also behave differently because
busy remains asserted. See the [investigation and source references](toki-turbo.txt).

R3's CPU interface, fast Blitter cadence, cache policy and quadrature mouse
support on joystick port 1 are retained. Turbo remains **60.2972184 MHz**.
The new version identifier is **PI FMG260915R460Mhz**.

## Verification scope

The CPU polling test connects the actual CPU bridge, Gary, Agnus arbiter,
Blitter, memory mapper and SRAM bridge. A controlled synthetic bitplane DMA
burst stalls the final write while the CPU polls DMACONR and immediately
programs another job. R3 corrupts memory in this case. It is a focused
contention test, not execution of Toki or graphics.library WaitBlit.

Independent bitmap results and original-Blitter DMA/address/data comparisons
remain required. Busy/interrupt comparisons account explicitly for the new
area-D completion policy, with unchanged line/no-D timing, one interrupt per
job and no spontaneous restart checked separately. Sprite tests cover all
eight channels and vertical-position wrap under Blitter contention.

Focused final tests pass:

- 31 CPU/DMA cases and 2,976 blits, including 1,152 priority bursts and 6,530
  starvation-relief slots. The R3 final-write race and omitted-wait controls
  both reproduce actual wrong memory data or lost writes.
- 1,152 independent golden/chained jobs, 10,306 destination writes and
  8,404,992 checked memory words, with original/current DMA/data equivalence.
- 256 channel/line/no-D jobs, 20,859 cycles and 3,565 DMA grants, including
  final-write holds with DMA and clock-enable disabled, unchanged line/no-D
  completion, exactly one interrupt per job and no spontaneous restart.

The initial private exploration also passed all 36 turbo burst combinations
(three phases, both priorities, byte/word polling and 1/4/8-slot bursts).
The maintained runner uses 12 selected burst combinations within its 31
cases. These are distinct counts; see [the test model](../tests/blitter/README.waitblit.txt).

The complete final regression suite passes. It also covers 100 physical
graphics DMA jobs, four sprite/scanout cases, 137 CPU/SRAM timing cases and
39,456 transfers, 36 bus-retirement cases, all 16 cache memory settings,
mouse/peripherals/host SPI, vendor clock startup and 196 phase-skew cases,
audit source guards and full-core elaboration. See [retained evidence](../reports/r4/README.txt).
These checks do not run a full Amiga software workload or model board-level
electrical behavior. Copper/Paula completion-consumer effects were reviewed
in the RTL; a new end-to-end Copper/interrupt-acknowledgment test was not added.

## Routed implementation

Selected build: `build/r4-60mhz-01`, ISE 14.7, XC3S400-4-PQ208,
area MAP, packing factor 95, PAR seed 1. Main, NORMAL, DCM-component and
focused external reports have zero timing errors. The phase audit passes
its separate setup/hold checks. Timing budgets and production constraints
are unchanged from R3.

A focused audit of busy, start, B-history initialization and Paula's Blitter
interrupt register checks 111,130 paths to their 13 physical input/control
pins. It partitions these four registers into a reporting group with the
same chip7 period and phase, retaining jitter and related clk28 paths. All
setup/hold checks pass; minimum slack across their incoming paths is
+11.550/+1.036 ns. The emitted examples through Blitter `done` have a minimum
setup slack of +19.656 ns; this subset is sampled from TRACE's worst-path
listing. The production PCF remains unchanged.

```sh
python3 scripts/audit_blitter_completion.py build/r4-60mhz-01 build/my-completion-audit
```

| Resource | R3 | R4 |
| --- | ---: | ---: |
| XST warnings, none filtered | 53 | 53 |
| Occupied slices / 3,584 | 3,550 | 3,550 |
| LUTs excluding route-throughs | 5,362 | 5,360 |
| Slice registers, including latches | 3,780 | 3,780 |
| Latches / BRAM / multipliers | 16 / 14 / 6 | 16 / 14 / 6 |

R4 uses two fewer LUTs, with the same 34 free slices. Remaining warnings
are described in the [warning audit](remaining-warnings.txt).

| Routed check | R3 slack | R4 slack |
| --- | ---: | ---: |
| 60.297 MHz CPU | +3.500 ns | +4.526 ns |
| 28 MHz chipset | +3.924 ns | +4.413 ns |
| 7 MHz chipset | +4.336 ns | +4.627 ns |
| Held cache word/selectors to CPU data, 16 ns budget | +1.908 ns | +2.143 ns |
| Registered turbo acknowledgment to DTACK, 6 ns budget | +0.052 ns | +0.130 ns |
| CPU byte strobes to lookup decision, 20 ns budget | +12.392 ns | +12.434 ns |

The external DTACK estimate remains narrow: +0.417 ns for bus acknowledgment
and +0.797 ns for cache acknowledgment after the 5 ns rated-part setup
reference and 0.5 ns engineering allowance. These are routed estimates,
not measured 60 MHz board margins. Held data has +17.307 ns after the same
reserves. SRAM data-path-only write-end/drive-release/read-enable separations
are +16.761 ns and +14.001 ns, excluding launch-clock differences and jitter.

Phase-sampler setup/hold margins are +13.822/+17.234 ns at its input and
+13.115/+18.679 ns at the following stage after documented clock allowances.
Local CPU completion takes at most 3.385 ns; CPU-pad data reaches the 32
Blitter mask registers within 14.040 ns including destination timing checks.
The nominal CPU write-release bound is 12.399 ns after custom Q0, or 9.399 ns
with zero AS-pin delay, with the same electrical/model limits as R3.

## Test image

Version: **PI FMG260915R460Mhz**. Turbo: **60.2972184 MHz**.

Published image: [MINIMIG1.BIN](../releases/r4-60mhz/MINIMIG1.BIN).
SHA256:

```text
6aae144b36db8b63af2ad413ad9a1ef71247f2326938124c1b6a0d6842e1fe1e
```

The [published release folder](../releases/r4-60mhz/README.txt) includes the
matching BIT file and the frozen source/report archive, cumulative changes
and checksums. The archive was prepared before hardware follow-up; current
board results are recorded here and in the release-folder README.
R3's image and package are preserved locally.

## Original Toki comparison procedure (investigation now closed)

Use the same Toki pit, slave dated 17.05.2013, 2 MB chip / 1.5 MB slow /
2 MB fast, and the same icon tooltypes as the R3 test. Cold-boot and compare
NORMAL and turbo. Repeat Workbench icon dragging, then other games and
Blitter/Copper demos. Use Delete to exit Toki if QuitKey has not been
overridden. R3 remains preserved for comparison.
