# R3: CPU bus completion and chipset phases

**2026-09-16 — promoted to favorite / preferred 60 MHz core.** The owner
retested the exact original R3 binary and reports that ArmourGeddon does not
crash, preferring it to later 60 MHz cores. Use the
[preferred image and provenance record](preferred-60mhz.txt). The binary
and original implementation evidence remain unchanged.

**Hardware follow-up:** the user reports that R3 eliminates the Workbench
corruption. Toki runs stably in the current test, but the character's feet
flicker in turbo only. This is a narrower remaining symptom; it does not
establish stability across other games or boards. See the
[Toki investigation](toki-turbo.txt).

R2 booted at both normal speed and 60.2972184 MHz on the user's SEC000 board.
Further testing found Workbench icon/font residue and game crashes. The user
then confirmed that a fresh NORMAL boot does not corrupt graphics: the
earlier NORMAL observation followed turbo operation. This fits corruption
persisting in memory after a speed switch. R2 therefore remains a useful
booting comparison image, not a demonstrated stable release.

R3 keeps the same CPU clock and native quadrature mouse support. It corrects
a reproduced turbo transaction failure and hardens the shared chipset phase
generator. The implementation notes below predate the hardware follow-ups
above; broader compatibility testing remains open.

## Changes

- **Retire completed CPU transfers locally.** At the end of a chipset slot,
  the CPU bridge now samples its own completion flag. Previously it relied on
  the acknowledgment making a round trip through the independent CPU clock.
  With conservative thresholds from the routed R2 paths, that return could
  miss the sampling edge and leave the old address/direction active for a
  following CPU transaction. The reproducer returns stale data or acknowledges
  a write without capturing it.
- **Acknowledge turbo writes at Q3.** SRAM still captures the word at Q2.
  The later acknowledgment keeps the CPU actively driving data through the
  custom-register capture at the following Q0. R2's early acknowledgment
  depended on input keepers to retain a released write word. Moving this
  acknowledgment alone is insufficient; it needs local retirement too.
- **Sample the 7 MHz clock away from its transition.** One falling-edge
  28 MHz register feeds the existing phase registers. The intended Q0–Q3
  sequence stays the same, while sampling gets approximately half a 28 MHz
  period instead of relying on the routed hold margin of coincident clocks.
  This applies to both normal and turbo modes. It is timing hardening;
  no board failure was specifically traced to this phase sampler.
- **Bypass the shared slow-RAM cache in the 512K+512K configuration.** ECS
  maps DMA accesses at 080000–0FFFFF onto the same physical bank that the CPU
  sees at C00000–C7FFFF. A DMA write can leave the CPU's cached copy stale.
  That slow bank now bypasses the cache in this configuration, including OCS
  conservatively; ROM caching and other memory configurations retain their
  policy. See the [alias details](cache-coherency-limit.txt).
- The core identifies itself with `260915R3`.

## Simulation evidence

- CPU/SRAM integration passes 137 timing cases and 39,456 transfers, including
  cache hits/misses, byte writes, delayed memory and DMA contention. Minimum
  modeled Q2-to-write-data-release interval is 77.902 ns.
- Focused bus-completion tests pass 36 cases and 14,624 transfers through real
  Gary/Agnus/Blitter mask registers and CPU/SRAM with acknowledgment delays.
  Removing the
  local completion fix or restoring the early write acknowledgment reproduces
  a functional failure. See [model and limits](../tests/README.cpu-bus-retirement.txt).
- Graphics DMA integration passes 100 jobs, 819,200 whole-memory word checks
  and 900 SRAM writes across normal/fast Blitter modes.
- The independent Blitter reference passes 1,152 jobs, 10,306 destination
  writes and 8,404,992 memory comparisons, including overlapping copies,
  masks, shifts, signed modulos and immediate restarts. Original and optimized
  Blitter state/data outputs remain equivalent. No Blitter arithmetic change
  was justified by this investigation.
- The phase sampler passes vendor DCM startup/mode tests and 196 skew cases
  with 50,176 phase comparisons, including explicit setup/hold checks.
- Cache/DMA tests pass 20 cases covering all 16 memory configurations, ECS/OCS,
  NORMAL/turbo, preserved ROM/slow cache hits and reset/configuration changes.
  Removing the shared-bank bypass reproduces stale data after a DMA write.

The complete regression suite passes, including existing mouse, peripheral,
cache, SRAM, clock and full-core elaboration checks. These are targeted
simulations and declared delay models, not a full Amiga software simulation
or a measurement of this board.

## Routed implementation

Selected build: `build/r3-60mhz-03`, ISE 14.7, XC3S400-4-PQ208,
area MAP, packing factor 95, PAR seed 1. Main, NORMAL, DCM-component and
focused external reports have **zero timing errors**. The dedicated phase
audit passes its separate setup/hold calculations and coverage checks.

| Resource | R2 | R3 |
| --- | ---: | ---: |
| XST warnings, none filtered | 54 | 53 |
| Occupied slices / 3,584 | 3,547 | 3,550 |
| LUTs excluding route-throughs | 5,360 | 5,362 |
| Slice registers, including latches | 3,779 | 3,780 |
| Latches / BRAM / multipliers | 16 / 14 / 6 | 16 / 14 / 6 |

R3 adds one register and two LUTs relative to R2, with 34 slices still free.
The original design occupied 3,558 slices and reported 250 XST warnings.
The remaining warnings are retained and described in the
[warning audit](remaining-warnings.txt).

| Routed check | Worst setup/max-delay slack |
| --- | ---: |
| 60.297 MHz CPU | +3.500 ns |
| 28 MHz chipset | +3.924 ns |
| 7 MHz chipset | +4.336 ns |
| Held cache word/selectors to CPU data, 16 ns budget | +1.908 ns |
| Registered turbo acknowledgment to DTACK, 6 ns budget | +0.052 ns |
| CPU byte strobes to lookup decision, 20 ns budget | +12.392 ns |

The local-completion path takes at most 3.429 ns against the 35.242 ns
Q3-to-Q0 interval. CPU-pad data reaches the 32 tested Blitter mask registers
within 14.739 ns including the destination timing check. The new phase
sampler's input setup/hold margins are +14.294/+16.827 ns; its following
stage has +13.705/+18.208 ns, after the documented additive clock allowances.

The external DTACK margin remains narrow: the routed estimate leaves
0.370 ns for bus acknowledgment and 0.701 ns for cache acknowledgment after
the 5 ns rated-part setup reference and 0.5 ns engineering allowance. These
are not guaranteed board margins at 60 MHz. The fixes address transaction
correctness; they do not establish that every routed path is faster than R2.
SRAM write-end/drive-release/read-enable separation remains positive under
the data-path-only model; PCB effects and actual device loading remain
outside that estimate.

Build 01 missed the 6 ns DTACK limit and generated no image. Build 02 passed
the main check but exposed the new memory-setting bits in the NORMAL cache
audit. Build 03 uses identical RTL/UCF and extends the existing source-checked
inactive-cache exceptions to those bits; no timing budget was relaxed.
See the [timing model](timing-model.txt) and retained reports in `reports/r3/`.

## Test image

Version: **PI FMG260915R360Mhz**. Turbo: **60.2972184 MHz**.

Image: [MINIMIG1.BIN](../releases/r3-60mhz/MINIMIG1.BIN).
SHA256:

```text
a6feb672529a822a1f2a9d2afb9f96021c56aaaa5d6194a987cbb167cf3675ab
```

The release package includes the matching BIT file, exact build inputs,
source commit, cumulative patch, reports and checksums. The package was
prepared before the hardware follow-up recorded above; its contents and
R3 bitstream remain unchanged.

## Hardware checks

Use the same Workbench icon-drag and game workloads that failed on R2.
First cold-boot directly into NORMAL and test there. Then cold-boot in turbo
and repeat. Record the game title and point of failure if a crash remains.
See the [hardware test guide](hardware-test.txt) for memory, reset, DMA and
mouse checks. R2 and its release package remain preserved separately.
