# R2: held CPU reads and native quadrature mouse

**Subsequent hardware feedback:** R2 boots at 60 MHz, but Workbench graphics
corruption and game crashes remain. A fresh NORMAL boot does not corrupt;
corruption can remain after switching from turbo. See [R3](r3-results.txt)
for the follow-up investigation. The measurements below describe R2 as built.

R2 keeps turbo at **60.2972184 MHz** and gives CPU reads more settling time.
The first test image (`5016887`) booted at normal speed but displayed a red
screen at 60 MHz on the user's board. The original core also failed at
60 MHz there. R2 addressed two demonstrated read-timing sensitivities and
was awaiting its first hardware test when this release was prepared.

## Changes

- Cache lookup allows an address-settling edge, then a RAM-read edge, then
  captures the tag decision and returned word. A following rising CPU edge
  acknowledges a hit. The result stays fixed until AS releases; misses cannot
  become late hits as the cache fills. Pending lookup blocks a competing
  chipset request.
- Uncached turbo reads acknowledge at Q3 instead of Q2, adding approximately
  35.2 ns of settling time. Writes still acknowledge their Q2 capture.
- Joystick port 1 accepts an Amiga quadrature mouse, with synchronized inputs,
  8-bit X/Y counters, left/right buttons, JOYTEST and native joystick decoding.
  Native movement or left click selects this port; PS/2 left click selects
  the existing PS/2 mouse. No menu or controller-firmware update is required.
- The CPU miss-acknowledgment register has an explicit board-specific placement
  to shorten its route to the DTACK pin. The 6 ns output budget remains enforced.
- The SPI version string includes `260915R2` to distinguish this test image.

The CPU clock is unchanged, but the extra waits reduce memory-access
throughput. The modeled cache hits take two to three wait cycles. This
candidate prioritizes timing margin over the previous shortest hit latency.

See [cache sequencing](cache-read-timing.txt), [CPU timing measurements](cpu-interface-timing.txt),
[native mouse wiring](quadrature-mouse.txt) and the [hardware test sequence](hardware-test.txt).

## Validation

The complete RTL regression suite passes, including 12,800 CPU cache-bus
transfers, 39,456 integrated CPU/SRAM transfers across 137 timing cases,
1,692 native mouse steps and 1,840 mouse/joystick checks. Existing Blitter
baseline equivalence, DMA, audio, peripheral, cache invalidation, SRAM write
hold, host SPI, clock-startup and full-core elaboration checks also pass.
The follow-up tests also exercise the inactive slow-mode lookup decision
while configuration inputs change. Mutation tests verify that timing
exceptions are withheld if the source conditions supporting them change.
The clock simulation emits two expected vendor startup-period warnings
before downstream DCM reset/lock sequencing completes.

The integrated test includes a synthetic 80 ns SRAM read budget, 33 ns CPU
write path, clock phase/forwarded-clock sweeps and DMA contention. These
are declared stress conditions, not measured delays of the user's board.
A Q2/Q3 control experiment and source hashes are retained in `reports/r2/`.

## Routed implementation

Selected build: `build/r2-60mhz-04`, ISE 14.7, XC3S400-4-PQ208,
area MAP with packing factor 95 and PAR seed 1. Main, slow-mode and DCM
component reports each have **zero timing errors**. The source-checked
slow-mode exceptions are described in [the timing model](timing-model.txt).
CPU/SRAM checks require nonzero path coverage before bitstream generation;
the report parser handles ISE's singular endpoint wording.

| Resource | Original | First image | R2 |
| --- | ---: | ---: | ---: |
| ISE synthesis warnings, none filtered | 250 | 54 | 54 |
| Occupied slices / 3,584 | 3,558 | 3,510 | 3,547 |
| LUTs excluding route-throughs | 5,359 | 5,313 | 5,360 |
| Slice registers, including latches | 3,757 | 3,736 | 3,779 |
| Inferred latches | 20 | 16 | 16 |
| BRAM blocks | 14 | 14 | 14 |
| Hardware multipliers | 8 | 6 | 6 |

The read pipeline and mouse counters cost 43 registers and 37 occupied slices
relative to the first image. R2 occupies 11 fewer slices than the original,
but the FPGA is nearly full, with 37 slices remaining.

| Routed constraint | Paths | Worst setup/max-delay slack |
| --- | ---: | ---: |
| CPU, 16.584513 ns period | 274 | +4.912 ns |
| Chipset 28 MHz | 1,529,047 | +5.332 ns |
| Chipset 7 MHz | 83,865,302 | +2.547 ns |
| Held cache word and selectors to CPU data, 16 ns | 48 | +0.465 ns |
| Registered turbo acknowledgment to DTACK, 6 ns | 2 | +0.256 ns |
| CPU byte strobes to lookup decision, 20 ns | 2 | +14.531 ns |

The placement constraint keeps the miss-acknowledgment register near DTACK
output logic. The measured worst held-word/selector path is 15.535 ns and
worst registered acknowledgment path is 5.744 ns. These FPGA budgets exclude
unknown board loading/skew and CPU behavior at 60 MHz. The
[interface audit](cpu-interface-timing.txt) records the forwarded-clock
relationship and SRAM hold measurements separately.

Translation reports one warning, MAP two, PAR three, and bitgen one. The
remaining categories match the first image's [warning audit](remaining-warnings.txt):
unused/constant interfaces, the intentional input latch, dense placement,
clock-net data loads, the existing SPI clock-pin routing override, and an
unused Amber BRAM output. They were not hidden or treated as proof of stability.

## Test image

Image: `releases/2026-09-15-r2-60mhz-test/MINIMIG1.BIN` (212,392 bytes).
Version: `PI FMG260915R260Mhz`. Binary SHA256:

```text
74cc58fdf8fef4db3b3c972a73bb5718f3ada28945740fb2b698b2795b12e5ae
```

The matching BIT payload equals the BIN exactly; the configuration header
identifies the XC3S400. `SOURCE-COMMIT.txt` in the release package identifies
the committed source, and `SHA256SUMS` covers the package contents. The first
image is preserved separately. The SD card was absent when R2 was prepared;
this candidate has not been copied to it or tested on the board.
