# CPU transaction completion: R3 audit

R3 retires turbo chipset transfers using the local Q3 completion signal at the
next Q0. It also acknowledges turbo writes at Q3, keeping the CPU write word
actively driven through custom-register capture. R2 could retain a completed
read for another chipset slot if its acknowledgment round trip through the
independent CPU clock missed Q0. A following write could then receive an
acknowledgment before any write capture.

The [R2 failure trace](../reports/r3/cpu-bus-retirement-r2-trace.txt) reproduces
that sequencing error using focused routed-delay thresholds. The
[regression description](../tests/README.cpu-bus-retirement.txt) explains the
model, protocol assumptions and its limits. The final suite passes **36 cases
and 14,624 transfers**, including actual Blitter mask registers, SRAM/cache/DMA,
short AS-high pulses between Q0 edges, both CPU modes and two mutations that
restore the failures.

## Final routed paths

Measured from `build/r3-60mhz-03`; the main implementation's related-clock PERIOD
constraints remain active. The additional loose FROM/TO constraints only obtain
path inventories from a copy of the routed design.

| Path | Paths / endpoints | Maximum reported delay |
| --- | ---: | ---: |
| Local completion `_ta_t1` → `l_as28m` | 1 / 1 | 3.429 ns |
| `_ta_t1` → first CPU synchronizer `_ta_t2` | 1 / 1 | 2.740 ns |
| `_ta_t2` → second CPU synchronizer `_ta_t` | 1 / 1 | 3.411 ns |
| `_ta_t` → chipset feedback `l_dtack` | 1 / 1 | 3.138 ns |
| CPU data pads → Blitter first/last-word masks | 32 / 32 | 14.739 ns |

TRACE reports zero errors and zero warnings for the focused inventory. These
FF-destination delays include the setup contribution; reported fastest paths
include hold-check adjustments. They are not bare wire propagation times.
The 3.429 ns local path fits within the 35.242 ns Q3-to-Q0 interval. The old
round trip still has variable CPU-clock latency, so its short individual paths
would not establish correct request retirement.

## Earliest custom-write release

Using the actual routed clock insertions, the nominal earliest CPU AS release
is **12.431 ns after custom-register Q0 capture** with the 3 ns CPU release
reference. Assuming zero CPU pin release delay instead still gives **9.431 ns**.
This is a protocol-based timing bound, not measured board hold time.

The calculation deliberately allows zero delay to the first CPU synchronizer.
From that first capture, the second synchronizer takes one CPU period; DTACK
recognition uses a following falling edge; completion takes another period.
The total is 2.5 CPU periods, adjusted for forwarded/local clock insertion and
the Q3-to-Q0 interval:

```
release after Q0 = 2.5 × Tcpu + CPU release delay
                + CPU clock-pad minimum − first-sync clock maximum
                + local-ACK clock minimum − custom clock maximum
                − Tchip28
```

The calculation uses nominal DCM phase/period and routed SDF min/max insertion.
It excludes DCM jitter, PCB effects and the overclocked CPU's electrical
behavior. Positive FPGA data-input propagation can extend data retention but is
not credited in this bound. Hardware testing is still needed to determine
whether these fixes resolve the reported graphics corruption and game crashes.

[Commands and input hashes](../reports/r3/cpu-retirement-commands.txt),
[focused paths](../reports/r3/cpu-retirement-focused.txt), and the
[clock calculation](../reports/r3/cpu-write-release-summary.json) preserve the
measurements. The reproduction script rejects mixed routed-design inputs.
