# Qualified CPU cache reads

The candidate replaces the live BRAM-output cache hit with a held result.
An address change can leave the previous word on the synchronous RAM outputs
until a CPU falling edge. If address input routing misses that edge, the old
word remains for another cycle. Comparing only the live tag does not detect
an old word at a different index with the same tag.

## Sequence

During a cacheable read with AS asserted:

1. The first CPU falling edge allows the external address path to settle.
2. The second falling edge samples the cache RAM address.
3. The third falling edge classifies the tag and valid bytes and captures
   the word in `cache_data_held`.
4. A hit selects that held word immediately. The next rising edge asserts
   the registered cache acknowledgment, `cache_hit_ack`.

The decision and data remain fixed until AS releases. A miss goes through
the chipset; filling the RAM during that access cannot turn it into a late
cache hit. Chipset requests remain blocked during lookup and for a classified
hit, including the half-cycle before its acknowledgment.

Reset, host ownership, slow mode, and cache bypass still inhibit cache use.
The byte-valid replacement/update rules and refill sampler are unchanged.
Uncached reads now acknowledge at Q3, allowing one more 28 MHz quarter-cycle
for returned data. Writes continue to acknowledge their Q2 capture.

This costs approximately two extra CPU clocks on a cache hit in the modeled
S0–S7 bus sequence, around 33.2 ns at 60.3 MHz. A miss can wait longer for
the next chipset slot. The Q3 change adds approximately 35.2 ns to uncached
read acknowledgment. These changes prioritize timing margin; they are not a
claim of increased instruction throughput or a proven red-screen fix.

## Validation and limits

`tests/tb_cpu_cache_bus_timing.v` uses address launch at S1, AS at S2,
termination sampling at the end of S4 plus full-clock waits, and read-data
sampling one clock after accepted termination. The sequence follows
[MC68000UM section 5.1](https://www.nxp.com/docs/en/reference-manual/MC68000UM.pdf).
It tests adjacent words, direct-mapped replacements, byte writes, consecutive
accesses, held data, and exclusion of simultaneous cache/chipset acknowledgment.

The test passes 2,560 accesses with zero modeled delays and with exploratory
clock/ACK/data/address delays of 4.4/6/16/9.1 ns. A temporary two-falling-edge
lookup failed that same delayed-address case: address F800F8 selected 180E
instead of 6C98. The three-edge implementation passes. These lumped delays
test ordering; they do not replace routed timing analysis or board measurement.

Run all five delay cases, totaling 12,800 bus transfers, with:

```sh
bash tests/run_cpu_cache_bus_regressions.sh
```

| Case | CPU clock delay | ACK delay | Read-data delay | Address-input delay | Memory delay |
| --- | ---: | ---: | ---: | ---: | ---: |
| Ideal | 0 | 0 | 0 | 0 | 20 |
| Delayed input | 4.4 | 6 | 16 | 9.1 | 20 |
| Delayed output | 4.4 | 15 | 21.1 | 9.1 | 30 |
| Early clock | 1.46 | 3 | 8 | 5 | 30 |
| Late clock | 8 | 10 | 10 | 9.1 | 30 |

All values are nanoseconds. The input delay is a simplified address-path
model; it does not reproduce every individual FPGA route or input skew.

The reset/invalidation and partial-byte cache regressions also pass with
quadrature chipset enables and the new acknowledgment latency. The corner
test also changes cache bypass and memory configuration during slow-mode
accesses and asserts that the lookup decision and hit acknowledgment stay
inactive, supporting the narrowly scoped slow-mode audit exception.
The CPU model
does not execute instructions, model metastability, or establish the installed
SEC000's electrical limits at 60 MHz. Confirm the actual candidate image on
hardware before treating it as a stable release.
