# ECS 512K chip + 512K slow cache coherency

R2 has a reproducible cache-coherency limitation when ECS is enabled and
`memory_config == 4'b0100` (512K chip plus 512K slow RAM).

| Access | Address range | Physical 512K bank |
| --- | --- | ---: |
| CPU slow RAM | C00000–C7FFFF | 2 |
| Agnus DMA | 080000–0FFFFF | 2 |

Gary deliberately creates this DMA alias. R2 caches CPU reads from the slow
range, but DMA writes neither update nor invalidate CPU cache entries.
Consequently a subsequent CPU read can return stale data from the cache.
Ordinary chip-RAM ranges are not cached. The other mapper configurations
keep the mapped DMA chip banks separate from the cacheable slow banks.

R3 disables caching of C00000–C7FFFF only when `memory_config == 0100`.
The same conservative rule applies in OCS, where this DMA alias is absent,
because the CPU bridge does not receive the ECS mode signal. OCS slow-memory
reads in this one configuration therefore lose their cache acceleration.
ROM caching remains enabled, as does slow-memory caching in every other
configuration. Memory mapping and DMA behavior are unchanged.

The integrated regression primes CPU C00400 with `18D7`, writes `DEAF`
through DMA080400, and reads C00400 again. R3 returns the updated SRAM word.
A temporary mutation removing the bypass reproduces R2's stale `18D7` result.
The NORMAL control also passes because NORMAL holds the cache invalid.

```sh
# Passing policy, DMA, configuration-transition and mutation regression:
python3 tests/repro_cache_dma_alias.py
# Only the ECS/OCS NORMAL controls:
python3 tests/repro_cache_dma_alias.py --slow
# Include source hashes and full simulator results:
python3 tests/repro_cache_dma_alias.py --log build/cache-alias-policy.log
```

The 20 cases reuse the integrated CPU/Gary/mapper/SRAM model. They check
all 16 turbo memory configurations, actual ROM/slow cache hits, the deliberate
OCS bypass, and ECS/OCS NORMAL controls. Sources are frozen during each run;
the runner rejects concurrent changes. The mutation must fail on wrong read
data after DMA, rather than merely an expected-hit assertion.

Memory configuration changes already require reset: the real OSD controller
copies its pending configuration only while reset is asserted. The top level
also routes reset to CPU cache invalidation. Reset starts the existing full
cache scrub before hits can resume. The transition test uses the actual OSD
reset latch to check `0101 -> 0100 -> DMA write -> 0101`, including rejection
of configuration changes outside reset and a fresh refill after leaving the
shared configuration. It supplies decoded pending commands directly; it does
not retest SPI command parsing. This reset contract prevents an old cached
word from resurfacing when slow-memory caching becomes enabled again.

The user subsequently confirmed that a fresh boot at normal 7 MHz has no
corruption; the earlier NORMAL residue followed turbo use. This fix addresses
a demonstrated stale-data case in the stated configuration. The simulations
do not establish which failure caused the observed graphics or game crashes.
