# Minimig 6 MB — S6 reliability candidate

This branch investigates the owner's report of delayed crashes at 40, 50
and 60 MHz with S5. FPGA **PI FMG260917S650Mhz** adds a full-cycle cache-refill
admission stage and registers the floppy FIFO full flag to shorten DMA
control timing. It uses the exact released **MM2609S5** ARM binary.
The default remains 50 MHz, with 20/30/40/50/60 MHz and Normal selectable.

See [the changes and validation record](docs/setup-s6.txt).
The [S6 test package](releases/setup-s6-test/README.txt) contains the selected
B/8 core, checksums, timing evidence and an S5 rollback binary. CPU timing
slack improves from 0.511 to 2.576 ns and chipset 28 MHz slack from 0.281 to
3.798 ns under the same constraints. The notes record the ACK/divider tradeoffs.
The released [S5 pair](releases/setup-s5/README.txt),
[S4 pair](releases/setup-s4/README.txt),
[R7 unified core](releases/r7-unified/README.txt) and
[preferred original R3 core](releases/r3-60mhz/README.txt) remain preserved.

S6 adds one CPU cycle to uncached reads; cache-hit timing is retained.
The compact OSD, storage support, clock selection, memory/cache policy and
S4 metadata-read fix are unchanged. Matching hashes verify that ARM MM2609S5
requires no update for this candidate.

Four independent ISE implementations can run concurrently:

```sh
python3 scripts/build_ise_sweep.py build/my-sweep HEAD
```

Selection requires main/Normal/component timing, independent route audits,
full regressions and long bus stress at all three reported unstable clocks.
Passing these checks does not establish the cause of the board crashes;
repeat the same workload on the selected candidate to assess reliability.
