Minimig1 Project Status (02/12/2025 - 11:28:21)
Project File: Minimig-PiStorm-6MB.xise Parser Errors: No Errors
Module Name: Minimig1 Implementation State: Placed and Routed
Target Device: xc3s400-4pq208
  • Errors:
 No Errors
Product Version:ISE 14.7
  • Warnings:
 264 Warnings (264 new)
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment: System Settings
  • Final Timing Score:
   
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Total Number Slice Registers 3,757 7,168 52%  
    Number used as Flip Flops 3,737      
    Number used as Latches 20      
Number of 4 input LUTs 5,359 7,168 74%  
Number of occupied Slices 3,582 3,584 99%  
    Number of Slices containing only related logic 3,582 3,582 100%  
    Number of Slices containing unrelated logic 0 3,582 0%  
Total Number of 4 input LUTs 5,690 7,168 79%  
    Number used as logic 5,048      
    Number used as a route-thru 331      
    Number used as 16x1 RAMs 29      
    Number used for Dual Port RAMs 262      
    Number used as Shift registers 20      
Number of bonded IOBs 140 141 99%  
Number of RAMB16s 14 16 87%  
Number of MULT18X18s 8 16 50%  
Number of BUFGMUXs 4 8 50%  
Number of DCMs 3 4 75%  
Average Fanout of Non-Clock Nets 3.24      
 
Performance Summary [-]
Final Timing Score:   Pinout Data: Pinout Report
Routing Results:   Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Feb 12 11:29:54 20250250 Warnings (250 new)48 Infos (48 new)
Translation ReportCurrentWed Feb 12 11:29:58 2025000
Map ReportCurrentWed Feb 12 11:30:04 2025013 Warnings (13 new)5 Infos (5 new)
Place and Route ReportCurrentWed Feb 12 11:30:11 202501 Warning (1 new)0
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 02/12/2025 - 12:43:37