Timing constraint: TS_R3_LOCAL_COMPLETION = MAXDELAY FROM TIMEGRP 
"R3_LOCAL_ACK" TO TIMEGRP "R3_LOCAL_REQUEST" 1000 ns DATAPATHONLY;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   5.065ns.
--------------------------------------------------------------------------------

Paths for end point CPU1/l_as28m (SLICE_X36Y38.SR), 1 path
--------------------------------------------------------------------------------
Slack (setup paths):    994.935ns (requirement - (data path - clock path skew + uncertainty))
  Source:               CPU1/_ta_t1 (FF)
  Destination:          CPU1/l_as28m (FF)
  Requirement:          1000.000ns
  Data Path Delay:      5.065ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: CPU1/_ta_t1 to CPU1/l_as28m
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X37Y38.YQ      Tcko                  0.720   CPU1/_ta_t1
                                                       CPU1/_ta_t1
    SLICE_X43Y38.G4      net (fanout=2)        1.067   CPU1/_ta_t1
    SLICE_X43Y38.X       Tif5x                 0.911   DENISE1/sprm0/sps1/datlb<7>
                                                       CPU1/l_as28m_or0000121
                                                       CPU1/l_as28m_or000012_f5
    SLICE_X36Y38.SR      net (fanout=1)        1.341   CPU1/l_as28m_or000012
    SLICE_X36Y38.CLK     Tsrck                 1.026   CPU1/l_as28m
                                                       CPU1/l_as28m
    -------------------------------------------------  ---------------------------
    Total                                      5.065ns (2.657ns logic, 2.408ns route)
                                                       (52.5% logic, 47.5% route)

--------------------------------------------------------------------------------

Fastest Paths: TS_R3_LOCAL_COMPLETION = MAXDELAY FROM TIMEGRP "R3_LOCAL_ACK" TO TIMEGRP "R3_LOCAL_REQUEST" 1000 ns DATAPATHONLY;
--------------------------------------------------------------------------------

Paths for end point CPU1/l_as28m (SLICE_X36Y38.SR), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      3.261ns (requirement - (clock path skew + uncertainty - data path))
  Source:               CPU1/_ta_t1 (FF)
  Destination:          CPU1/l_as28m (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.261ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 422.904ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: CPU1/_ta_t1 to CPU1/l_as28m
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X37Y38.YQ      Tcko                  0.576   CPU1/_ta_t1
                                                       CPU1/_ta_t1
    SLICE_X43Y38.G4      net (fanout=2)        0.854   CPU1/_ta_t1
    SLICE_X43Y38.X       Tif5x                 0.729   DENISE1/sprm0/sps1/datlb<7>
                                                       CPU1/l_as28m_or0000121
                                                       CPU1/l_as28m_or000012_f5
    SLICE_X36Y38.SR      net (fanout=1)        1.073   CPU1/l_as28m_or000012
    SLICE_X36Y38.CLK     Tcksr       (-Th)    -0.029   CPU1/l_as28m
                                                       CPU1/l_as28m
    -------------------------------------------------  ---------------------------
    Total                                      3.261ns (1.334ns logic, 1.927ns route)
                                                       (40.9% logic, 59.1% route)

--------------------------------------------------------------------------------

================================================================================

Timing constraint: TS_R3_FIRST_SYNC = MAXDELAY FROM TIMEGRP "R3_LOCAL_ACK" TO 
TIMEGRP "R3_CPU_SYNC1" 1000 ns DATAPATHONLY;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   2.362ns.
--------------------------------------------------------------------------------

Paths for end point CPU1/_ta_t2 (SLICE_X40Y38.CE), 1 path
--------------------------------------------------------------------------------
Slack (setup paths):    997.638ns (requirement - (data path - clock path skew + uncertainty))
  Source:               CPU1/_ta_t1 (FF)
  Destination:          CPU1/_ta_t2 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      2.362ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising
  Destination Clock:    cpu_clk_OBUF rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: CPU1/_ta_t1 to CPU1/_ta_t2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X37Y38.YQ      Tcko                  0.720   CPU1/_ta_t1
                                                       CPU1/_ta_t1
    SLICE_X40Y38.CE      net (fanout=2)        1.040   CPU1/_ta_t1
    SLICE_X40Y38.CLK     Tceck                 0.602   CPU1/_ta_t2
                                                       CPU1/_ta_t2
    -------------------------------------------------  ---------------------------
    Total                                      2.362ns (1.322ns logic, 1.040ns route)
                                                       (56.0% logic, 44.0% route)

--------------------------------------------------------------------------------

Fastest Paths: TS_R3_FIRST_SYNC = MAXDELAY FROM TIMEGRP "R3_LOCAL_ACK" TO TIMEGRP "R3_CPU_SYNC1" 1000 ns DATAPATHONLY;
--------------------------------------------------------------------------------

Paths for end point CPU1/_ta_t2 (SLICE_X40Y38.CE), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      1.408ns (requirement - (clock path skew + uncertainty - data path))
  Source:               CPU1/_ta_t1 (FF)
  Destination:          CPU1/_ta_t2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.408ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising
  Destination Clock:    cpu_clk_OBUF rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: CPU1/_ta_t1 to CPU1/_ta_t2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X37Y38.YQ      Tcko                  0.576   CPU1/_ta_t1
                                                       CPU1/_ta_t1
    SLICE_X40Y38.CE      net (fanout=2)        0.832   CPU1/_ta_t1
    SLICE_X40Y38.CLK     Tckce       (-Th)     0.000   CPU1/_ta_t2
                                                       CPU1/_ta_t2
    -------------------------------------------------  ---------------------------
    Total                                      1.408ns (0.576ns logic, 0.832ns route)
                                                       (40.9% logic, 59.1% route)

--------------------------------------------------------------------------------

================================================================================

Timing constraint: TS_R3_SECOND_SYNC = MAXDELAY FROM TIMEGRP "R3_CPU_SYNC1" TO 
TIMEGRP "R3_CPU_SYNC2" 1000 ns DATAPATHONLY;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   3.914ns.
--------------------------------------------------------------------------------

Paths for end point CPU1/_ta_t (SLICE_X45Y40.CE), 1 path
--------------------------------------------------------------------------------
Slack (setup paths):    996.086ns (requirement - (data path - clock path skew + uncertainty))
  Source:               CPU1/_ta_t2 (FF)
  Destination:          CPU1/_ta_t (FF)
  Requirement:          1000.000ns
  Data Path Delay:      3.914ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         cpu_clk_OBUF rising at 0.000ns
  Destination Clock:    cpu_clk_OBUF rising at 16.584ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: CPU1/_ta_t2 to CPU1/_ta_t
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X40Y38.YQ      Tcko                  0.720   CPU1/_ta_t2
                                                       CPU1/_ta_t2
    SLICE_X45Y40.CE      net (fanout=1)        2.592   CPU1/_ta_t2
    SLICE_X45Y40.CLK     Tceck                 0.602   CPU1/_ta_t
                                                       CPU1/_ta_t
    -------------------------------------------------  ---------------------------
    Total                                      3.914ns (1.322ns logic, 2.592ns route)
                                                       (33.8% logic, 66.2% route)

--------------------------------------------------------------------------------

Fastest Paths: TS_R3_SECOND_SYNC = MAXDELAY FROM TIMEGRP "R3_CPU_SYNC1" TO TIMEGRP "R3_CPU_SYNC2" 1000 ns DATAPATHONLY;
--------------------------------------------------------------------------------

Paths for end point CPU1/_ta_t (SLICE_X45Y40.CE), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      2.649ns (requirement - (clock path skew + uncertainty - data path))
  Source:               CPU1/_ta_t2 (FF)
  Destination:          CPU1/_ta_t (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.649ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         cpu_clk_OBUF rising at 0.000ns
  Destination Clock:    cpu_clk_OBUF rising at 0.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: CPU1/_ta_t2 to CPU1/_ta_t
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X40Y38.YQ      Tcko                  0.576   CPU1/_ta_t2
                                                       CPU1/_ta_t2
    SLICE_X45Y40.CE      net (fanout=1)        2.073   CPU1/_ta_t2
    SLICE_X45Y40.CLK     Tckce       (-Th)     0.000   CPU1/_ta_t
                                                       CPU1/_ta_t
    -------------------------------------------------  ---------------------------
    Total                                      2.649ns (0.576ns logic, 2.073ns route)
                                                       (21.7% logic, 78.3% route)

--------------------------------------------------------------------------------

================================================================================

Timing constraint: TS_R3_RETURN_ACK = MAXDELAY FROM TIMEGRP "R3_CPU_SYNC2" TO 
TIMEGRP "R3_CPU_FEEDBACK" 1000 ns DATAPATHONLY;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   2.410ns.
--------------------------------------------------------------------------------

Paths for end point CPU1/l_dtack (SLICE_X42Y41.F2), 1 path
--------------------------------------------------------------------------------
Slack (setup paths):    997.590ns (requirement - (data path - clock path skew + uncertainty))
  Source:               CPU1/_ta_t (FF)
  Destination:          CPU1/l_dtack (FF)
  Requirement:          1000.000ns
  Data Path Delay:      2.410ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         cpu_clk_OBUF rising
  Destination Clock:    clk rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: CPU1/_ta_t to CPU1/l_dtack
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X45Y40.YQ      Tcko                  0.720   CPU1/_ta_t
                                                       CPU1/_ta_t
    SLICE_X42Y41.F2      net (fanout=3)        1.000   CPU1/_ta_t
    SLICE_X42Y41.CLK     Tfck                  0.690   l_dtack
                                                       CPU1/private_internal_dtack
                                                       CPU1/l_dtack
    -------------------------------------------------  ---------------------------
    Total                                      2.410ns (1.410ns logic, 1.000ns route)
                                                       (58.5% logic, 41.5% route)

--------------------------------------------------------------------------------

Fastest Paths: TS_R3_RETURN_ACK = MAXDELAY FROM TIMEGRP "R3_CPU_SYNC2" TO TIMEGRP "R3_CPU_FEEDBACK" 1000 ns DATAPATHONLY;
--------------------------------------------------------------------------------

Paths for end point CPU1/l_dtack (SLICE_X42Y41.F2), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      1.482ns (requirement - (clock path skew + uncertainty - data path))
  Source:               CPU1/_ta_t (FF)
  Destination:          CPU1/l_dtack (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.482ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         cpu_clk_OBUF rising
  Destination Clock:    clk rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: CPU1/_ta_t to CPU1/l_dtack
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X45Y40.YQ      Tcko                  0.576   CPU1/_ta_t
                                                       CPU1/_ta_t
    SLICE_X42Y41.F2      net (fanout=3)        0.800   CPU1/_ta_t
    SLICE_X42Y41.CLK     Tckf        (-Th)    -0.106   l_dtack
                                                       CPU1/private_internal_dtack
                                                       CPU1/l_dtack
    -------------------------------------------------  ---------------------------
    Total                                      1.482ns (0.682ns logic, 0.800ns route)
                                                       (46.0% logic, 54.0% route)

--------------------------------------------------------------------------------

================================================================================

Timing constraint: TS_R3_CUSTOM_DATA = MAXDELAY FROM TIMEGRP "CPU_DATA" TO 
TIMEGRP "R3_CUSTOM_MASKS" 1000 ns DATAPATHONLY;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 32 paths analyzed, 32 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is  14.625ns.
--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_4 (SLICE_X47Y33.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  985.375ns (requirement - data path)
  Source:               cpu_data<4> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_4 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      14.625ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<4> to AGNUS1/bl1/bltafwm_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P166.I               Tiopi                 1.918   cpu_data<4>
                                                       cpu_data<4>
                                                       cpu_data_4_IOBUF/IBUF
    SLICE_X33Y14.F2      net (fanout=19)       4.340   N957
    SLICE_X33Y14.X       Tilo                  0.551   DENISE1/sprm0/sps3/hstart<6>
                                                       gary_cpu_data_in<4>1
    SLICE_X35Y10.G1      net (fanout=6)        2.968   gary_cpu_data_in<4>
    SLICE_X35Y10.Y       Tilo                  0.551   AGNUS1/bl1/bltadat<4>
                                                       GARY1/custom_data_in<4>1
    SLICE_X47Y33.BY      net (fanout=93)       4.036   custom_data_in<4>
    SLICE_X47Y33.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<3>
                                                       AGNUS1/bl1/bltafwm_4
    -------------------------------------------------  ---------------------------
    Total                                     14.625ns (3.281ns logic, 11.344ns route)
                                                       (22.4% logic, 77.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_10 (SLICE_X48Y31.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  985.762ns (requirement - data path)
  Source:               cpu_data<10> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_10 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      14.238ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<10> to AGNUS1/bl1/bltalwm_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P147.I               Tiopi                 1.918   cpu_data<10>
                                                       cpu_data<10>
                                                       cpu_data_10_IOBUF/IBUF
    SLICE_X26Y15.F3      net (fanout=22)       4.913   N951
    SLICE_X26Y15.X       Tilo                  0.608   AGNUS1/bpd1/dmaena_delayed<1>
                                                       gary_cpu_data_in<10>1
    SLICE_X30Y6.F2       net (fanout=3)        1.557   gary_cpu_data_in<10>
    SLICE_X30Y6.X        Tilo                  0.608   AGNUS1/bl1/height<10>
                                                       GARY1/custom_data_in<10>1
    SLICE_X48Y31.BX      net (fanout=75)       4.431   custom_data_in<10>
    SLICE_X48Y31.CLK     Tdick                 0.203   AGNUS1/bl1/bltalwm<10>
                                                       AGNUS1/bl1/bltalwm_10
    -------------------------------------------------  ---------------------------
    Total                                     14.238ns (3.337ns logic, 10.901ns route)
                                                       (23.4% logic, 76.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_10 (SLICE_X49Y33.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  985.909ns (requirement - data path)
  Source:               cpu_data<10> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_10 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      14.091ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<10> to AGNUS1/bl1/bltafwm_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P147.I               Tiopi                 1.918   cpu_data<10>
                                                       cpu_data<10>
                                                       cpu_data_10_IOBUF/IBUF
    SLICE_X26Y15.F3      net (fanout=22)       4.913   N951
    SLICE_X26Y15.X       Tilo                  0.608   AGNUS1/bpd1/dmaena_delayed<1>
                                                       gary_cpu_data_in<10>1
    SLICE_X30Y6.F2       net (fanout=3)        1.557   gary_cpu_data_in<10>
    SLICE_X30Y6.X        Tilo                  0.608   AGNUS1/bl1/height<10>
                                                       GARY1/custom_data_in<10>1
    SLICE_X49Y33.BY      net (fanout=75)       4.226   custom_data_in<10>
    SLICE_X49Y33.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<10>
                                                       AGNUS1/bl1/bltafwm_10
    -------------------------------------------------  ---------------------------
    Total                                     14.091ns (3.395ns logic, 10.696ns route)
                                                       (24.1% logic, 75.9% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_8 (SLICE_X42Y33.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  986.066ns (requirement - data path)
  Source:               cpu_data<8> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_8 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      13.934ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<8> to AGNUS1/bl1/bltafwm_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P152.I               Tiopi                 1.918   cpu_data<8>
                                                       cpu_data<8>
                                                       cpu_data_8_IOBUF/IBUF
    SLICE_X27Y10.G2      net (fanout=22)       5.851   N953
    SLICE_X27Y10.Y       Tilo                  0.551   _l_data_14
                                                       gary_cpu_data_in<8>1
    SLICE_X29Y18.F2      net (fanout=3)        2.145   gary_cpu_data_in<8>
    SLICE_X29Y18.X       Tilo                  0.551   AGNUS1/bl1/bltadat<8>
                                                       GARY1/custom_data_in<8>1
    SLICE_X42Y33.BY      net (fanout=72)       2.657   custom_data_in<8>
    SLICE_X42Y33.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<8>
                                                       AGNUS1/bl1/bltafwm_8
    -------------------------------------------------  ---------------------------
    Total                                     13.934ns (3.281ns logic, 10.653ns route)
                                                       (23.5% logic, 76.5% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_8 (SLICE_X42Y29.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  986.409ns (requirement - data path)
  Source:               cpu_data<8> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_8 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      13.591ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<8> to AGNUS1/bl1/bltalwm_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P152.I               Tiopi                 1.918   cpu_data<8>
                                                       cpu_data<8>
                                                       cpu_data_8_IOBUF/IBUF
    SLICE_X27Y10.G2      net (fanout=22)       5.851   N953
    SLICE_X27Y10.Y       Tilo                  0.551   _l_data_14
                                                       gary_cpu_data_in<8>1
    SLICE_X29Y18.F2      net (fanout=3)        2.145   gary_cpu_data_in<8>
    SLICE_X29Y18.X       Tilo                  0.551   AGNUS1/bl1/bltadat<8>
                                                       GARY1/custom_data_in<8>1
    SLICE_X42Y29.BY      net (fanout=72)       2.314   custom_data_in<8>
    SLICE_X42Y29.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<8>
                                                       AGNUS1/bl1/bltalwm_8
    -------------------------------------------------  ---------------------------
    Total                                     13.591ns (3.281ns logic, 10.310ns route)
                                                       (24.1% logic, 75.9% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_4 (SLICE_X46Y31.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  986.452ns (requirement - data path)
  Source:               cpu_data<4> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_4 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      13.548ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<4> to AGNUS1/bl1/bltalwm_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P166.I               Tiopi                 1.918   cpu_data<4>
                                                       cpu_data<4>
                                                       cpu_data_4_IOBUF/IBUF
    SLICE_X33Y14.F2      net (fanout=19)       4.340   N957
    SLICE_X33Y14.X       Tilo                  0.551   DENISE1/sprm0/sps3/hstart<6>
                                                       gary_cpu_data_in<4>1
    SLICE_X35Y10.G1      net (fanout=6)        2.968   gary_cpu_data_in<4>
    SLICE_X35Y10.Y       Tilo                  0.551   AGNUS1/bl1/bltadat<4>
                                                       GARY1/custom_data_in<4>1
    SLICE_X46Y31.BY      net (fanout=93)       2.959   custom_data_in<4>
    SLICE_X46Y31.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<4>
                                                       AGNUS1/bl1/bltalwm_4
    -------------------------------------------------  ---------------------------
    Total                                     13.548ns (3.281ns logic, 10.267ns route)
                                                       (24.2% logic, 75.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_5 (SLICE_X45Y25.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  986.670ns (requirement - data path)
  Source:               cpu_data<5> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_5 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      13.330ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<5> to AGNUS1/bl1/bltalwm_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P165.I               Tiopi                 1.918   cpu_data<5>
                                                       cpu_data<5>
                                                       cpu_data_5_IOBUF/IBUF
    SLICE_X34Y16.G2      net (fanout=19)       3.821   N956
    SLICE_X34Y16.Y       Tilo                  0.608   DENISE1/hpos<8>
                                                       gary_cpu_data_in<5>1
    SLICE_X35Y20.F2      net (fanout=4)        3.015   gary_cpu_data_in<5>
    SLICE_X35Y20.X       Tilo                  0.551   AGNUS1/bl1/bltadat<5>
                                                       GARY1/custom_data_in<5>1
    SLICE_X45Y25.BX      net (fanout=89)       3.214   custom_data_in<5>
    SLICE_X45Y25.CLK     Tdick                 0.203   AGNUS1/bl1/bltalwm<5>
                                                       AGNUS1/bl1/bltalwm_5
    -------------------------------------------------  ---------------------------
    Total                                     13.330ns (3.280ns logic, 10.050ns route)
                                                       (24.6% logic, 75.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_12 (SLICE_X53Y34.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  986.940ns (requirement - data path)
  Source:               cpu_data<12> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_12 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      13.060ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<12> to AGNUS1/bl1/bltafwm_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P141.I               Tiopi                 1.918   cpu_data<12>
                                                       cpu_data<12>
                                                       cpu_data_12_IOBUF/IBUF
    SLICE_X27Y17.F2      net (fanout=23)       4.483   N949
    SLICE_X27Y17.X       Tilo                  0.551   AGNUS1/bpd1/dmaena_delayed<0>
                                                       gary_cpu_data_in<12>1
    SLICE_X26Y12.F1      net (fanout=4)        0.897   gary_cpu_data_in<12>
    SLICE_X26Y12.X       Tilo                  0.608   AGNUS1/bl1/height<12>
                                                       GARY1/custom_data_in<12>1
    SLICE_X53Y34.BY      net (fanout=70)       4.342   custom_data_in<12>
    SLICE_X53Y34.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<11>
                                                       AGNUS1/bl1/bltafwm_12
    -------------------------------------------------  ---------------------------
    Total                                     13.060ns (3.338ns logic, 9.722ns route)
                                                       (25.6% logic, 74.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_3 (SLICE_X47Y33.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  986.950ns (requirement - data path)
  Source:               cpu_data<3> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_3 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      13.050ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<3> to AGNUS1/bl1/bltafwm_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P162.I               Tiopi                 1.918   cpu_data<3>
                                                       cpu_data<3>
                                                       cpu_data_3_IOBUF/IBUF
    SLICE_X32Y13.G3      net (fanout=20)       5.081   N958
    SLICE_X32Y13.Y       Tilo                  0.608   AGNUS1/bpd1/bplcon0<2>
                                                       gary_cpu_data_in<3>1
    SLICE_X28Y22.G1      net (fanout=5)        1.452   gary_cpu_data_in<3>
    SLICE_X28Y22.Y       Tilo                  0.608   AGNUS1/bl1/bltadat<3>
                                                       GARY1/custom_data_in<3>1
    SLICE_X47Y33.BX      net (fanout=93)       3.180   custom_data_in<3>
    SLICE_X47Y33.CLK     Tdick                 0.203   AGNUS1/bl1/bltafwm<3>
                                                       AGNUS1/bl1/bltafwm_3
    -------------------------------------------------  ---------------------------
    Total                                     13.050ns (3.337ns logic, 9.713ns route)
                                                       (25.6% logic, 74.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_13 (SLICE_X49Y35.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  987.011ns (requirement - data path)
  Source:               cpu_data<13> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_13 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      12.989ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<13> to AGNUS1/bl1/bltafwm_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P139.I               Tiopi                 1.918   cpu_data<13>
                                                       cpu_data<13>
                                                       cpu_data_13_IOBUF/IBUF
    SLICE_X24Y14.F2      net (fanout=21)       4.911   N948
    SLICE_X24Y14.X       Tilo                  0.608   gary_cpu_data_in<13>
                                                       gary_cpu_data_in<13>1
    SLICE_X29Y12.F2      net (fanout=4)        1.723   gary_cpu_data_in<13>
    SLICE_X29Y12.X       Tilo                  0.551   AGNUS1/bl1/height<13>
                                                       GARY1/custom_data_in<13>1
    SLICE_X49Y35.BX      net (fanout=70)       3.075   custom_data_in<13>
    SLICE_X49Y35.CLK     Tdick                 0.203   AGNUS1/bl1/bltafwm<13>
                                                       AGNUS1/bl1/bltafwm_13
    -------------------------------------------------  ---------------------------
    Total                                     12.989ns (3.280ns logic, 9.709ns route)
                                                       (25.3% logic, 74.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_7 (SLICE_X44Y31.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  987.172ns (requirement - data path)
  Source:               cpu_data<7> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_7 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      12.828ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<7> to AGNUS1/bl1/bltafwm_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P155.I               Tiopi                 1.918   cpu_data<7>
                                                       cpu_data<7>
                                                       cpu_data_7_IOBUF/IBUF
    SLICE_X30Y19.G2      net (fanout=22)       5.828   N954
    SLICE_X30Y19.Y       Tilo                  0.608   DENISE1/hdiwstrt<2>
                                                       gary_cpu_data_in<7>1
    SLICE_X33Y18.F4      net (fanout=5)        0.363   gary_cpu_data_in<7>
    SLICE_X33Y18.X       Tilo                  0.551   AGNUS1/bl1/bltadat<7>
                                                       GARY1/custom_data_in<7>1
    SLICE_X44Y31.BY      net (fanout=84)       3.299   custom_data_in<7>
    SLICE_X44Y31.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<5>
                                                       AGNUS1/bl1/bltafwm_7
    -------------------------------------------------  ---------------------------
    Total                                     12.828ns (3.338ns logic, 9.490ns route)
                                                       (26.0% logic, 74.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_11 (SLICE_X53Y34.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  987.175ns (requirement - data path)
  Source:               cpu_data<11> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_11 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      12.825ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<11> to AGNUS1/bl1/bltafwm_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P144.I               Tiopi                 1.918   cpu_data<11>
                                                       cpu_data<11>
                                                       cpu_data_11_IOBUF/IBUF
    SLICE_X26Y15.G3      net (fanout=21)       3.788   N950
    SLICE_X26Y15.Y       Tilo                  0.608   AGNUS1/bpd1/dmaena_delayed<1>
                                                       gary_cpu_data_in<11>1
    SLICE_X28Y13.F1      net (fanout=3)        0.626   gary_cpu_data_in<11>
    SLICE_X28Y13.X       Tilo                  0.608   AGNUS1/bl1/height<11>
                                                       GARY1/custom_data_in<11>1
    SLICE_X53Y34.BX      net (fanout=72)       5.074   custom_data_in<11>
    SLICE_X53Y34.CLK     Tdick                 0.203   AGNUS1/bl1/bltafwm<11>
                                                       AGNUS1/bl1/bltafwm_11
    -------------------------------------------------  ---------------------------
    Total                                     12.825ns (3.337ns logic, 9.488ns route)
                                                       (26.0% logic, 74.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_3 (SLICE_X47Y28.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  987.231ns (requirement - data path)
  Source:               cpu_data<3> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_3 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      12.769ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<3> to AGNUS1/bl1/bltalwm_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P162.I               Tiopi                 1.918   cpu_data<3>
                                                       cpu_data<3>
                                                       cpu_data_3_IOBUF/IBUF
    SLICE_X32Y13.G3      net (fanout=20)       5.081   N958
    SLICE_X32Y13.Y       Tilo                  0.608   AGNUS1/bpd1/bplcon0<2>
                                                       gary_cpu_data_in<3>1
    SLICE_X28Y22.G1      net (fanout=5)        1.452   gary_cpu_data_in<3>
    SLICE_X28Y22.Y       Tilo                  0.608   AGNUS1/bl1/bltadat<3>
                                                       GARY1/custom_data_in<3>1
    SLICE_X47Y28.BY      net (fanout=93)       2.841   custom_data_in<3>
    SLICE_X47Y28.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<2>
                                                       AGNUS1/bl1/bltalwm_3
    -------------------------------------------------  ---------------------------
    Total                                     12.769ns (3.395ns logic, 9.374ns route)
                                                       (26.6% logic, 73.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_13 (SLICE_X49Y30.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  987.293ns (requirement - data path)
  Source:               cpu_data<13> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_13 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      12.707ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<13> to AGNUS1/bl1/bltalwm_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P139.I               Tiopi                 1.918   cpu_data<13>
                                                       cpu_data<13>
                                                       cpu_data_13_IOBUF/IBUF
    SLICE_X24Y14.F2      net (fanout=21)       4.911   N948
    SLICE_X24Y14.X       Tilo                  0.608   gary_cpu_data_in<13>
                                                       gary_cpu_data_in<13>1
    SLICE_X29Y12.F2      net (fanout=4)        1.723   gary_cpu_data_in<13>
    SLICE_X29Y12.X       Tilo                  0.551   AGNUS1/bl1/height<13>
                                                       GARY1/custom_data_in<13>1
    SLICE_X49Y30.BY      net (fanout=70)       2.735   custom_data_in<13>
    SLICE_X49Y30.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<12>
                                                       AGNUS1/bl1/bltalwm_13
    -------------------------------------------------  ---------------------------
    Total                                     12.707ns (3.338ns logic, 9.369ns route)
                                                       (26.3% logic, 73.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_15 (SLICE_X49Y36.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  987.545ns (requirement - data path)
  Source:               cpu_data<15> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_15 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      12.455ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<15> to AGNUS1/bl1/bltafwm_15
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P135.I               Tiopi                 1.918   cpu_data<15>
                                                       cpu_data<15>
                                                       cpu_data_15_IOBUF/IBUF
    SLICE_X27Y15.G1      net (fanout=27)       4.785   N946
    SLICE_X27Y15.Y       Tilo                  0.551   DENISE1/sprm0/sps0/datla<9>
                                                       gary_cpu_data_in<15>1
    SLICE_X24Y21.F1      net (fanout=5)        1.084   gary_cpu_data_in<15>
    SLICE_X24Y21.X       Tilo                  0.608   AGNUS1/bpd1/vdiwstop<7>
                                                       GARY1/custom_data_in<15>1
    SLICE_X49Y36.BY      net (fanout=131)      3.248   custom_data_in<15>
    SLICE_X49Y36.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<15>
                                                       AGNUS1/bl1/bltafwm_15
    -------------------------------------------------  ---------------------------
    Total                                     12.455ns (3.338ns logic, 9.117ns route)
                                                       (26.8% logic, 73.2% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_5 (SLICE_X44Y31.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  987.604ns (requirement - data path)
  Source:               cpu_data<5> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_5 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      12.396ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<5> to AGNUS1/bl1/bltafwm_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P165.I               Tiopi                 1.918   cpu_data<5>
                                                       cpu_data<5>
                                                       cpu_data_5_IOBUF/IBUF
    SLICE_X34Y16.G2      net (fanout=19)       3.821   N956
    SLICE_X34Y16.Y       Tilo                  0.608   DENISE1/hpos<8>
                                                       gary_cpu_data_in<5>1
    SLICE_X35Y20.F2      net (fanout=4)        3.015   gary_cpu_data_in<5>
    SLICE_X35Y20.X       Tilo                  0.551   AGNUS1/bl1/bltadat<5>
                                                       GARY1/custom_data_in<5>1
    SLICE_X44Y31.BX      net (fanout=89)       2.280   custom_data_in<5>
    SLICE_X44Y31.CLK     Tdick                 0.203   AGNUS1/bl1/bltafwm<5>
                                                       AGNUS1/bl1/bltafwm_5
    -------------------------------------------------  ---------------------------
    Total                                     12.396ns (3.280ns logic, 9.116ns route)
                                                       (26.5% logic, 73.5% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_14 (SLICE_X49Y35.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  987.965ns (requirement - data path)
  Source:               cpu_data<14> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_14 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      12.035ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<14> to AGNUS1/bl1/bltafwm_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P137.I               Tiopi                 1.918   cpu_data<14>
                                                       cpu_data<14>
                                                       cpu_data_14_IOBUF/IBUF
    SLICE_X27Y15.F1      net (fanout=22)       4.628   N947
    SLICE_X27Y15.X       Tilo                  0.551   DENISE1/sprm0/sps0/datla<9>
                                                       gary_cpu_data_in<14>1
    SLICE_X30Y13.F2      net (fanout=4)        1.259   gary_cpu_data_in<14>
    SLICE_X30Y13.X       Tilo                  0.608   AGNUS1/bl1/height<14>
                                                       GARY1/custom_data_in<14>1
    SLICE_X49Y35.BY      net (fanout=69)       2.810   custom_data_in<14>
    SLICE_X49Y35.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<13>
                                                       AGNUS1/bl1/bltafwm_14
    -------------------------------------------------  ---------------------------
    Total                                     12.035ns (3.338ns logic, 8.697ns route)
                                                       (27.7% logic, 72.3% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_12 (SLICE_X49Y30.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.195ns (requirement - data path)
  Source:               cpu_data<12> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_12 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.805ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<12> to AGNUS1/bl1/bltalwm_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P141.I               Tiopi                 1.918   cpu_data<12>
                                                       cpu_data<12>
                                                       cpu_data_12_IOBUF/IBUF
    SLICE_X27Y17.F2      net (fanout=23)       4.483   N949
    SLICE_X27Y17.X       Tilo                  0.551   AGNUS1/bpd1/dmaena_delayed<0>
                                                       gary_cpu_data_in<12>1
    SLICE_X26Y12.F1      net (fanout=4)        0.897   gary_cpu_data_in<12>
    SLICE_X26Y12.X       Tilo                  0.608   AGNUS1/bl1/height<12>
                                                       GARY1/custom_data_in<12>1
    SLICE_X49Y30.BX      net (fanout=70)       3.145   custom_data_in<12>
    SLICE_X49Y30.CLK     Tdick                 0.203   AGNUS1/bl1/bltalwm<12>
                                                       AGNUS1/bl1/bltalwm_12
    -------------------------------------------------  ---------------------------
    Total                                     11.805ns (3.280ns logic, 8.525ns route)
                                                       (27.8% logic, 72.2% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_7 (SLICE_X44Y27.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.263ns (requirement - data path)
  Source:               cpu_data<7> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_7 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.737ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<7> to AGNUS1/bl1/bltalwm_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P155.I               Tiopi                 1.918   cpu_data<7>
                                                       cpu_data<7>
                                                       cpu_data_7_IOBUF/IBUF
    SLICE_X30Y19.G2      net (fanout=22)       5.828   N954
    SLICE_X30Y19.Y       Tilo                  0.608   DENISE1/hdiwstrt<2>
                                                       gary_cpu_data_in<7>1
    SLICE_X33Y18.F4      net (fanout=5)        0.363   gary_cpu_data_in<7>
    SLICE_X33Y18.X       Tilo                  0.551   AGNUS1/bl1/bltadat<7>
                                                       GARY1/custom_data_in<7>1
    SLICE_X44Y27.BX      net (fanout=84)       2.266   custom_data_in<7>
    SLICE_X44Y27.CLK     Tdick                 0.203   AGNUS1/bl1/bltalwm<7>
                                                       AGNUS1/bl1/bltalwm_7
    -------------------------------------------------  ---------------------------
    Total                                     11.737ns (3.280ns logic, 8.457ns route)
                                                       (27.9% logic, 72.1% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_11 (SLICE_X48Y31.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.300ns (requirement - data path)
  Source:               cpu_data<11> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_11 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.700ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<11> to AGNUS1/bl1/bltalwm_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P144.I               Tiopi                 1.918   cpu_data<11>
                                                       cpu_data<11>
                                                       cpu_data_11_IOBUF/IBUF
    SLICE_X26Y15.G3      net (fanout=21)       3.788   N950
    SLICE_X26Y15.Y       Tilo                  0.608   AGNUS1/bpd1/dmaena_delayed<1>
                                                       gary_cpu_data_in<11>1
    SLICE_X28Y13.F1      net (fanout=3)        0.626   gary_cpu_data_in<11>
    SLICE_X28Y13.X       Tilo                  0.608   AGNUS1/bl1/height<11>
                                                       GARY1/custom_data_in<11>1
    SLICE_X48Y31.BY      net (fanout=72)       3.891   custom_data_in<11>
    SLICE_X48Y31.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<10>
                                                       AGNUS1/bl1/bltalwm_11
    -------------------------------------------------  ---------------------------
    Total                                     11.700ns (3.395ns logic, 8.305ns route)
                                                       (29.0% logic, 71.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_6 (SLICE_X40Y26.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.309ns (requirement - data path)
  Source:               cpu_data<6> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_6 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.691ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<6> to AGNUS1/bl1/bltafwm_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P161.I               Tiopi                 1.918   cpu_data<6>
                                                       cpu_data<6>
                                                       cpu_data_6_IOBUF/IBUF
    SLICE_X33Y14.G2      net (fanout=19)       4.297   N955
    SLICE_X33Y14.Y       Tilo                  0.551   DENISE1/sprm0/sps3/hstart<6>
                                                       gary_cpu_data_in<6>1
    SLICE_X25Y18.F2      net (fanout=4)        1.385   gary_cpu_data_in<6>
    SLICE_X25Y18.X       Tilo                  0.551   AGNUS1/bl1/bltadat<6>
                                                       GARY1/custom_data_in<6>1
    SLICE_X40Y26.BY      net (fanout=91)       2.728   custom_data_in<6>
    SLICE_X40Y26.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<6>
                                                       AGNUS1/bl1/bltafwm_6
    -------------------------------------------------  ---------------------------
    Total                                     11.691ns (3.281ns logic, 8.410ns route)
                                                       (28.1% logic, 71.9% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_0 (SLICE_X47Y22.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.339ns (requirement - data path)
  Source:               cpu_data<0> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_0 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.661ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<0> to AGNUS1/bl1/bltalwm_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P150.I               Tiopi                 1.918   cpu_data<0>
                                                       cpu_data<0>
                                                       cpu_data_0_IOBUF/IBUF
    SLICE_X30Y19.F4      net (fanout=21)       3.742   N961
    SLICE_X30Y19.X       Tilo                  0.608   DENISE1/hdiwstrt<2>
                                                       gary_cpu_data_in<0>1
    SLICE_X31Y13.G4      net (fanout=3)        0.737   gary_cpu_data_in<0>
    SLICE_X31Y13.Y       Tilo                  0.551   AGNUS1/bl1/bltadat<0>
                                                       GARY1/custom_data_in<0>2
    SLICE_X47Y22.BY      net (fanout=92)       3.844   custom_data_in<0>
    SLICE_X47Y22.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<0>
                                                       AGNUS1/bl1/bltalwm_0
    -------------------------------------------------  ---------------------------
    Total                                     11.661ns (3.338ns logic, 8.323ns route)
                                                       (28.6% logic, 71.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_6 (SLICE_X45Y25.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.403ns (requirement - data path)
  Source:               cpu_data<6> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_6 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.597ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<6> to AGNUS1/bl1/bltalwm_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P161.I               Tiopi                 1.918   cpu_data<6>
                                                       cpu_data<6>
                                                       cpu_data_6_IOBUF/IBUF
    SLICE_X33Y14.G2      net (fanout=19)       4.297   N955
    SLICE_X33Y14.Y       Tilo                  0.551   DENISE1/sprm0/sps3/hstart<6>
                                                       gary_cpu_data_in<6>1
    SLICE_X25Y18.F2      net (fanout=4)        1.385   gary_cpu_data_in<6>
    SLICE_X25Y18.X       Tilo                  0.551   AGNUS1/bl1/bltadat<6>
                                                       GARY1/custom_data_in<6>1
    SLICE_X45Y25.BY      net (fanout=91)       2.634   custom_data_in<6>
    SLICE_X45Y25.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<5>
                                                       AGNUS1/bl1/bltalwm_6
    -------------------------------------------------  ---------------------------
    Total                                     11.597ns (3.281ns logic, 8.316ns route)
                                                       (28.3% logic, 71.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_9 (SLICE_X45Y35.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.405ns (requirement - data path)
  Source:               cpu_data<9> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_9 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.595ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<9> to AGNUS1/bl1/bltafwm_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P149.I               Tiopi                 1.918   cpu_data<9>
                                                       cpu_data<9>
                                                       cpu_data_9_IOBUF/IBUF
    SLICE_X30Y16.G2      net (fanout=22)       3.707   N952
    SLICE_X30Y16.Y       Tilo                  0.608   DENISE1/sprm0/sps5/datlb<14>
                                                       gary_cpu_data_in<9>1
    SLICE_X30Y18.F2      net (fanout=3)        0.518   gary_cpu_data_in<9>
    SLICE_X30Y18.X       Tilo                  0.608   AGNUS1/bl1/bltadat<9>
                                                       GARY1/custom_data_in<9>1
    SLICE_X45Y35.BY      net (fanout=73)       3.975   custom_data_in<9>
    SLICE_X45Y35.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<9>
                                                       AGNUS1/bl1/bltafwm_9
    -------------------------------------------------  ---------------------------
    Total                                     11.595ns (3.395ns logic, 8.200ns route)
                                                       (29.3% logic, 70.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_15 (SLICE_X49Y31.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.523ns (requirement - data path)
  Source:               cpu_data<15> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_15 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.477ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<15> to AGNUS1/bl1/bltalwm_15
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P135.I               Tiopi                 1.918   cpu_data<15>
                                                       cpu_data<15>
                                                       cpu_data_15_IOBUF/IBUF
    SLICE_X27Y15.G1      net (fanout=27)       4.785   N946
    SLICE_X27Y15.Y       Tilo                  0.551   DENISE1/sprm0/sps0/datla<9>
                                                       gary_cpu_data_in<15>1
    SLICE_X24Y21.F1      net (fanout=5)        1.084   gary_cpu_data_in<15>
    SLICE_X24Y21.X       Tilo                  0.608   AGNUS1/bpd1/vdiwstop<7>
                                                       GARY1/custom_data_in<15>1
    SLICE_X49Y31.BY      net (fanout=131)      2.270   custom_data_in<15>
    SLICE_X49Y31.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<15>
                                                       AGNUS1/bl1/bltalwm_15
    -------------------------------------------------  ---------------------------
    Total                                     11.477ns (3.338ns logic, 8.139ns route)
                                                       (29.1% logic, 70.9% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_1 (SLICE_X47Y27.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.664ns (requirement - data path)
  Source:               cpu_data<1> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_1 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.336ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<1> to AGNUS1/bl1/bltafwm_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P154.I               Tiopi                 1.918   cpu_data<1>
                                                       cpu_data<1>
                                                       cpu_data_1_IOBUF/IBUF
    SLICE_X30Y10.F4      net (fanout=21)       4.500   N960
    SLICE_X30Y10.X       Tilo                  0.608   AGNUS1/bl1/height<6>
                                                       gary_cpu_data_in<1>1
    SLICE_X31Y11.G4      net (fanout=5)        0.058   gary_cpu_data_in<1>
    SLICE_X31Y11.Y       Tilo                  0.551   AGNUS1/bl1/bltadat<1>
                                                       GARY1/custom_data_in<1>1
    SLICE_X47Y27.BY      net (fanout=96)       3.440   custom_data_in<1>
    SLICE_X47Y27.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<1>
                                                       AGNUS1/bl1/bltafwm_1
    -------------------------------------------------  ---------------------------
    Total                                     11.336ns (3.338ns logic, 7.998ns route)
                                                       (29.4% logic, 70.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_1 (SLICE_X47Y24.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.999ns (requirement - data path)
  Source:               cpu_data<1> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_1 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.001ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<1> to AGNUS1/bl1/bltalwm_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P154.I               Tiopi                 1.918   cpu_data<1>
                                                       cpu_data<1>
                                                       cpu_data_1_IOBUF/IBUF
    SLICE_X30Y10.F4      net (fanout=21)       4.500   N960
    SLICE_X30Y10.X       Tilo                  0.608   AGNUS1/bl1/height<6>
                                                       gary_cpu_data_in<1>1
    SLICE_X31Y11.G4      net (fanout=5)        0.058   gary_cpu_data_in<1>
    SLICE_X31Y11.Y       Tilo                  0.551   AGNUS1/bl1/bltadat<1>
                                                       GARY1/custom_data_in<1>1
    SLICE_X47Y24.BY      net (fanout=96)       3.105   custom_data_in<1>
    SLICE_X47Y24.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<1>
                                                       AGNUS1/bl1/bltalwm_1
    -------------------------------------------------  ---------------------------
    Total                                     11.001ns (3.338ns logic, 7.663ns route)
                                                       (30.3% logic, 69.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_2 (SLICE_X47Y28.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  989.148ns (requirement - data path)
  Source:               cpu_data<2> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_2 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      10.852ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<2> to AGNUS1/bl1/bltalwm_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P156.I               Tiopi                 1.918   cpu_data<2>
                                                       cpu_data<2>
                                                       cpu_data_2_IOBUF/IBUF
    SLICE_X22Y21.F1      net (fanout=20)       4.050   N959
    SLICE_X22Y21.X       Tilo                  0.608   gary_cpu_data_in<2>
                                                       gary_cpu_data_in<2>1
    SLICE_X23Y23.F4      net (fanout=3)        0.359   gary_cpu_data_in<2>
    SLICE_X23Y23.X       Tilo                  0.551   AGNUS1/bl1/bltadat<2>
                                                       GARY1/custom_data_in<2>1
    SLICE_X47Y28.BX      net (fanout=99)       3.163   custom_data_in<2>
    SLICE_X47Y28.CLK     Tdick                 0.203   AGNUS1/bl1/bltalwm<2>
                                                       AGNUS1/bl1/bltalwm_2
    -------------------------------------------------  ---------------------------
    Total                                     10.852ns (3.280ns logic, 7.572ns route)
                                                       (30.2% logic, 69.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_0 (SLICE_X43Y31.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  989.252ns (requirement - data path)
  Source:               cpu_data<0> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_0 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      10.748ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<0> to AGNUS1/bl1/bltafwm_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P150.I               Tiopi                 1.918   cpu_data<0>
                                                       cpu_data<0>
                                                       cpu_data_0_IOBUF/IBUF
    SLICE_X30Y19.F4      net (fanout=21)       3.742   N961
    SLICE_X30Y19.X       Tilo                  0.608   DENISE1/hdiwstrt<2>
                                                       gary_cpu_data_in<0>1
    SLICE_X31Y13.G4      net (fanout=3)        0.737   gary_cpu_data_in<0>
    SLICE_X31Y13.Y       Tilo                  0.551   AGNUS1/bl1/bltadat<0>
                                                       GARY1/custom_data_in<0>2
    SLICE_X43Y31.BX      net (fanout=92)       2.989   custom_data_in<0>
    SLICE_X43Y31.CLK     Tdick                 0.203   AGNUS1/bl1/bltafwm<0>
                                                       AGNUS1/bl1/bltafwm_0
    -------------------------------------------------  ---------------------------
    Total                                     10.748ns (3.280ns logic, 7.468ns route)
                                                       (30.5% logic, 69.5% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_14 (SLICE_X30Y23.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  989.350ns (requirement - data path)
  Source:               cpu_data<14> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_14 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      10.650ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<14> to AGNUS1/bl1/bltalwm_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P137.I               Tiopi                 1.918   cpu_data<14>
                                                       cpu_data<14>
                                                       cpu_data_14_IOBUF/IBUF
    SLICE_X27Y15.F1      net (fanout=22)       4.628   N947
    SLICE_X27Y15.X       Tilo                  0.551   DENISE1/sprm0/sps0/datla<9>
                                                       gary_cpu_data_in<14>1
    SLICE_X30Y13.F2      net (fanout=4)        1.259   gary_cpu_data_in<14>
    SLICE_X30Y13.X       Tilo                  0.608   AGNUS1/bl1/height<14>
                                                       GARY1/custom_data_in<14>1
    SLICE_X30Y23.BY      net (fanout=69)       1.425   custom_data_in<14>
    SLICE_X30Y23.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<14>
                                                       AGNUS1/bl1/bltalwm_14
    -------------------------------------------------  ---------------------------
    Total                                     10.650ns (3.338ns logic, 7.312ns route)
                                                       (31.3% logic, 68.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_2 (SLICE_X43Y31.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  989.439ns (requirement - data path)
  Source:               cpu_data<2> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_2 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      10.561ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<2> to AGNUS1/bl1/bltafwm_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P156.I               Tiopi                 1.918   cpu_data<2>
                                                       cpu_data<2>
                                                       cpu_data_2_IOBUF/IBUF
    SLICE_X22Y21.F1      net (fanout=20)       4.050   N959
    SLICE_X22Y21.X       Tilo                  0.608   gary_cpu_data_in<2>
                                                       gary_cpu_data_in<2>1
    SLICE_X23Y23.F4      net (fanout=3)        0.359   gary_cpu_data_in<2>
    SLICE_X23Y23.X       Tilo                  0.551   AGNUS1/bl1/bltadat<2>
                                                       GARY1/custom_data_in<2>1
    SLICE_X43Y31.BY      net (fanout=99)       2.814   custom_data_in<2>
    SLICE_X43Y31.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<0>
                                                       AGNUS1/bl1/bltafwm_2
    -------------------------------------------------  ---------------------------
    Total                                     10.561ns (3.338ns logic, 7.223ns route)
                                                       (31.6% logic, 68.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_9 (SLICE_X44Y27.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  990.422ns (requirement - data path)
  Source:               cpu_data<9> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_9 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      9.578ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<9> to AGNUS1/bl1/bltalwm_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P149.I               Tiopi                 1.918   cpu_data<9>
                                                       cpu_data<9>
                                                       cpu_data_9_IOBUF/IBUF
    SLICE_X30Y16.G2      net (fanout=22)       3.707   N952
    SLICE_X30Y16.Y       Tilo                  0.608   DENISE1/sprm0/sps5/datlb<14>
                                                       gary_cpu_data_in<9>1
    SLICE_X30Y18.F2      net (fanout=3)        0.518   gary_cpu_data_in<9>
    SLICE_X30Y18.X       Tilo                  0.608   AGNUS1/bl1/bltadat<9>
                                                       GARY1/custom_data_in<9>1
    SLICE_X44Y27.BY      net (fanout=73)       1.958   custom_data_in<9>
    SLICE_X44Y27.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<7>
                                                       AGNUS1/bl1/bltalwm_9
    -------------------------------------------------  ---------------------------
    Total                                      9.578ns (3.395ns logic, 6.183ns route)
                                                       (35.4% logic, 64.6% route)

--------------------------------------------------------------------------------

Fastest Paths: TS_R3_CUSTOM_DATA = MAXDELAY FROM TIMEGRP "CPU_DATA" TO TIMEGRP "R3_CUSTOM_MASKS" 1000 ns DATAPATHONLY;
--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_9 (SLICE_X44Y27.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      7.210ns (data path)
  Source:               cpu_data<9> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_9 (FF)
  Requirement:          0.000ns
  Data Path Delay:      7.210ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<9> to AGNUS1/bl1/bltalwm_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P149.I               Tiopi                 1.530   cpu_data<9>
                                                       cpu_data<9>
                                                       cpu_data_9_IOBUF/IBUF
    SLICE_X30Y16.G2      net (fanout=22)       2.965   N952
    SLICE_X30Y16.Y       Tilo                  0.486   DENISE1/sprm0/sps5/datlb<14>
                                                       gary_cpu_data_in<9>1
    SLICE_X30Y18.F2      net (fanout=3)        0.414   gary_cpu_data_in<9>
    SLICE_X30Y18.X       Tilo                  0.486   AGNUS1/bl1/bltadat<9>
                                                       GARY1/custom_data_in<9>1
    SLICE_X44Y27.BY      net (fanout=73)       1.566   custom_data_in<9>
    SLICE_X44Y27.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<7>
                                                       AGNUS1/bl1/bltalwm_9
    -------------------------------------------------  ---------------------------
    Total                                      7.210ns (2.265ns logic, 4.945ns route)
                                                       (31.4% logic, 68.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_2 (SLICE_X43Y31.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      7.998ns (data path)
  Source:               cpu_data<2> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      7.998ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<2> to AGNUS1/bl1/bltafwm_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P156.I               Tiopi                 1.530   cpu_data<2>
                                                       cpu_data<2>
                                                       cpu_data_2_IOBUF/IBUF
    SLICE_X22Y21.F1      net (fanout=20)       3.240   N959
    SLICE_X22Y21.X       Tilo                  0.486   gary_cpu_data_in<2>
                                                       gary_cpu_data_in<2>1
    SLICE_X23Y23.F4      net (fanout=3)        0.287   gary_cpu_data_in<2>
    SLICE_X23Y23.X       Tilo                  0.441   AGNUS1/bl1/bltadat<2>
                                                       GARY1/custom_data_in<2>1
    SLICE_X43Y31.BY      net (fanout=99)       2.251   custom_data_in<2>
    SLICE_X43Y31.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<0>
                                                       AGNUS1/bl1/bltafwm_2
    -------------------------------------------------  ---------------------------
    Total                                      7.998ns (2.220ns logic, 5.778ns route)
                                                       (27.8% logic, 72.2% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_14 (SLICE_X30Y23.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.070ns (data path)
  Source:               cpu_data<14> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_14 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.070ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<14> to AGNUS1/bl1/bltalwm_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P137.I               Tiopi                 1.530   cpu_data<14>
                                                       cpu_data<14>
                                                       cpu_data_14_IOBUF/IBUF
    SLICE_X27Y15.F1      net (fanout=22)       3.703   N947
    SLICE_X27Y15.X       Tilo                  0.441   DENISE1/sprm0/sps0/datla<9>
                                                       gary_cpu_data_in<14>1
    SLICE_X30Y13.F2      net (fanout=4)        1.007   gary_cpu_data_in<14>
    SLICE_X30Y13.X       Tilo                  0.486   AGNUS1/bl1/height<14>
                                                       GARY1/custom_data_in<14>1
    SLICE_X30Y23.BY      net (fanout=69)       1.140   custom_data_in<14>
    SLICE_X30Y23.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<14>
                                                       AGNUS1/bl1/bltalwm_14
    -------------------------------------------------  ---------------------------
    Total                                      8.070ns (2.220ns logic, 5.850ns route)
                                                       (27.5% logic, 72.5% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_0 (SLICE_X43Y31.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.148ns (data path)
  Source:               cpu_data<0> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.148ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<0> to AGNUS1/bl1/bltafwm_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P150.I               Tiopi                 1.530   cpu_data<0>
                                                       cpu_data<0>
                                                       cpu_data_0_IOBUF/IBUF
    SLICE_X30Y19.F4      net (fanout=21)       2.994   N961
    SLICE_X30Y19.X       Tilo                  0.486   DENISE1/hdiwstrt<2>
                                                       gary_cpu_data_in<0>1
    SLICE_X31Y13.G4      net (fanout=3)        0.589   gary_cpu_data_in<0>
    SLICE_X31Y13.Y       Tilo                  0.441   AGNUS1/bl1/bltadat<0>
                                                       GARY1/custom_data_in<0>2
    SLICE_X43Y31.BX      net (fanout=92)       2.391   custom_data_in<0>
    SLICE_X43Y31.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltafwm<0>
                                                       AGNUS1/bl1/bltafwm_0
    -------------------------------------------------  ---------------------------
    Total                                      8.148ns (2.174ns logic, 5.974ns route)
                                                       (26.7% logic, 73.3% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_2 (SLICE_X47Y28.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.231ns (data path)
  Source:               cpu_data<2> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.231ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<2> to AGNUS1/bl1/bltalwm_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P156.I               Tiopi                 1.530   cpu_data<2>
                                                       cpu_data<2>
                                                       cpu_data_2_IOBUF/IBUF
    SLICE_X22Y21.F1      net (fanout=20)       3.240   N959
    SLICE_X22Y21.X       Tilo                  0.486   gary_cpu_data_in<2>
                                                       gary_cpu_data_in<2>1
    SLICE_X23Y23.F4      net (fanout=3)        0.287   gary_cpu_data_in<2>
    SLICE_X23Y23.X       Tilo                  0.441   AGNUS1/bl1/bltadat<2>
                                                       GARY1/custom_data_in<2>1
    SLICE_X47Y28.BX      net (fanout=99)       2.530   custom_data_in<2>
    SLICE_X47Y28.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltalwm<2>
                                                       AGNUS1/bl1/bltalwm_2
    -------------------------------------------------  ---------------------------
    Total                                      8.231ns (2.174ns logic, 6.057ns route)
                                                       (26.4% logic, 73.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_1 (SLICE_X47Y24.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.351ns (data path)
  Source:               cpu_data<1> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.351ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<1> to AGNUS1/bl1/bltalwm_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P154.I               Tiopi                 1.530   cpu_data<1>
                                                       cpu_data<1>
                                                       cpu_data_1_IOBUF/IBUF
    SLICE_X30Y10.F4      net (fanout=21)       3.600   N960
    SLICE_X30Y10.X       Tilo                  0.486   AGNUS1/bl1/height<6>
                                                       gary_cpu_data_in<1>1
    SLICE_X31Y11.G4      net (fanout=5)        0.047   gary_cpu_data_in<1>
    SLICE_X31Y11.Y       Tilo                  0.441   AGNUS1/bl1/bltadat<1>
                                                       GARY1/custom_data_in<1>1
    SLICE_X47Y24.BY      net (fanout=96)       2.484   custom_data_in<1>
    SLICE_X47Y24.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<1>
                                                       AGNUS1/bl1/bltalwm_1
    -------------------------------------------------  ---------------------------
    Total                                      8.351ns (2.220ns logic, 6.131ns route)
                                                       (26.6% logic, 73.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_1 (SLICE_X47Y27.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.619ns (data path)
  Source:               cpu_data<1> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.619ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<1> to AGNUS1/bl1/bltafwm_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P154.I               Tiopi                 1.530   cpu_data<1>
                                                       cpu_data<1>
                                                       cpu_data_1_IOBUF/IBUF
    SLICE_X30Y10.F4      net (fanout=21)       3.600   N960
    SLICE_X30Y10.X       Tilo                  0.486   AGNUS1/bl1/height<6>
                                                       gary_cpu_data_in<1>1
    SLICE_X31Y11.G4      net (fanout=5)        0.047   gary_cpu_data_in<1>
    SLICE_X31Y11.Y       Tilo                  0.441   AGNUS1/bl1/bltadat<1>
                                                       GARY1/custom_data_in<1>1
    SLICE_X47Y27.BY      net (fanout=96)       2.752   custom_data_in<1>
    SLICE_X47Y27.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<1>
                                                       AGNUS1/bl1/bltafwm_1
    -------------------------------------------------  ---------------------------
    Total                                      8.619ns (2.220ns logic, 6.399ns route)
                                                       (25.8% logic, 74.2% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_15 (SLICE_X49Y31.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.731ns (data path)
  Source:               cpu_data<15> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_15 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.731ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<15> to AGNUS1/bl1/bltalwm_15
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P135.I               Tiopi                 1.530   cpu_data<15>
                                                       cpu_data<15>
                                                       cpu_data_15_IOBUF/IBUF
    SLICE_X27Y15.G1      net (fanout=27)       3.828   N946
    SLICE_X27Y15.Y       Tilo                  0.441   DENISE1/sprm0/sps0/datla<9>
                                                       gary_cpu_data_in<15>1
    SLICE_X24Y21.F1      net (fanout=5)        0.867   gary_cpu_data_in<15>
    SLICE_X24Y21.X       Tilo                  0.486   AGNUS1/bpd1/vdiwstop<7>
                                                       GARY1/custom_data_in<15>1
    SLICE_X49Y31.BY      net (fanout=131)      1.816   custom_data_in<15>
    SLICE_X49Y31.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<15>
                                                       AGNUS1/bl1/bltalwm_15
    -------------------------------------------------  ---------------------------
    Total                                      8.731ns (2.220ns logic, 6.511ns route)
                                                       (25.4% logic, 74.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_9 (SLICE_X45Y35.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.824ns (data path)
  Source:               cpu_data<9> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_9 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.824ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<9> to AGNUS1/bl1/bltafwm_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P149.I               Tiopi                 1.530   cpu_data<9>
                                                       cpu_data<9>
                                                       cpu_data_9_IOBUF/IBUF
    SLICE_X30Y16.G2      net (fanout=22)       2.965   N952
    SLICE_X30Y16.Y       Tilo                  0.486   DENISE1/sprm0/sps5/datlb<14>
                                                       gary_cpu_data_in<9>1
    SLICE_X30Y18.F2      net (fanout=3)        0.414   gary_cpu_data_in<9>
    SLICE_X30Y18.X       Tilo                  0.486   AGNUS1/bl1/bltadat<9>
                                                       GARY1/custom_data_in<9>1
    SLICE_X45Y35.BY      net (fanout=73)       3.180   custom_data_in<9>
    SLICE_X45Y35.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<9>
                                                       AGNUS1/bl1/bltafwm_9
    -------------------------------------------------  ---------------------------
    Total                                      8.824ns (2.265ns logic, 6.559ns route)
                                                       (25.7% logic, 74.3% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_6 (SLICE_X45Y25.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.828ns (data path)
  Source:               cpu_data<6> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.828ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<6> to AGNUS1/bl1/bltalwm_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P161.I               Tiopi                 1.530   cpu_data<6>
                                                       cpu_data<6>
                                                       cpu_data_6_IOBUF/IBUF
    SLICE_X33Y14.G2      net (fanout=19)       3.438   N955
    SLICE_X33Y14.Y       Tilo                  0.441   DENISE1/sprm0/sps3/hstart<6>
                                                       gary_cpu_data_in<6>1
    SLICE_X25Y18.F2      net (fanout=4)        1.108   gary_cpu_data_in<6>
    SLICE_X25Y18.X       Tilo                  0.441   AGNUS1/bl1/bltadat<6>
                                                       GARY1/custom_data_in<6>1
    SLICE_X45Y25.BY      net (fanout=91)       2.107   custom_data_in<6>
    SLICE_X45Y25.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<5>
                                                       AGNUS1/bl1/bltalwm_6
    -------------------------------------------------  ---------------------------
    Total                                      8.828ns (2.175ns logic, 6.653ns route)
                                                       (24.6% logic, 75.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_0 (SLICE_X47Y22.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.878ns (data path)
  Source:               cpu_data<0> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.878ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<0> to AGNUS1/bl1/bltalwm_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P150.I               Tiopi                 1.530   cpu_data<0>
                                                       cpu_data<0>
                                                       cpu_data_0_IOBUF/IBUF
    SLICE_X30Y19.F4      net (fanout=21)       2.994   N961
    SLICE_X30Y19.X       Tilo                  0.486   DENISE1/hdiwstrt<2>
                                                       gary_cpu_data_in<0>1
    SLICE_X31Y13.G4      net (fanout=3)        0.589   gary_cpu_data_in<0>
    SLICE_X31Y13.Y       Tilo                  0.441   AGNUS1/bl1/bltadat<0>
                                                       GARY1/custom_data_in<0>2
    SLICE_X47Y22.BY      net (fanout=92)       3.075   custom_data_in<0>
    SLICE_X47Y22.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<0>
                                                       AGNUS1/bl1/bltalwm_0
    -------------------------------------------------  ---------------------------
    Total                                      8.878ns (2.220ns logic, 6.658ns route)
                                                       (25.0% logic, 75.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_6 (SLICE_X40Y26.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.904ns (data path)
  Source:               cpu_data<6> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.904ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<6> to AGNUS1/bl1/bltafwm_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P161.I               Tiopi                 1.530   cpu_data<6>
                                                       cpu_data<6>
                                                       cpu_data_6_IOBUF/IBUF
    SLICE_X33Y14.G2      net (fanout=19)       3.438   N955
    SLICE_X33Y14.Y       Tilo                  0.441   DENISE1/sprm0/sps3/hstart<6>
                                                       gary_cpu_data_in<6>1
    SLICE_X25Y18.F2      net (fanout=4)        1.108   gary_cpu_data_in<6>
    SLICE_X25Y18.X       Tilo                  0.441   AGNUS1/bl1/bltadat<6>
                                                       GARY1/custom_data_in<6>1
    SLICE_X40Y26.BY      net (fanout=91)       2.183   custom_data_in<6>
    SLICE_X40Y26.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<6>
                                                       AGNUS1/bl1/bltafwm_6
    -------------------------------------------------  ---------------------------
    Total                                      8.904ns (2.175ns logic, 6.729ns route)
                                                       (24.4% logic, 75.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_11 (SLICE_X48Y31.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.909ns (data path)
  Source:               cpu_data<11> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_11 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.909ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<11> to AGNUS1/bl1/bltalwm_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P144.I               Tiopi                 1.530   cpu_data<11>
                                                       cpu_data<11>
                                                       cpu_data_11_IOBUF/IBUF
    SLICE_X26Y15.G3      net (fanout=21)       3.030   N950
    SLICE_X26Y15.Y       Tilo                  0.486   AGNUS1/bpd1/dmaena_delayed<1>
                                                       gary_cpu_data_in<11>1
    SLICE_X28Y13.F1      net (fanout=3)        0.501   gary_cpu_data_in<11>
    SLICE_X28Y13.X       Tilo                  0.486   AGNUS1/bl1/height<11>
                                                       GARY1/custom_data_in<11>1
    SLICE_X48Y31.BY      net (fanout=72)       3.113   custom_data_in<11>
    SLICE_X48Y31.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<10>
                                                       AGNUS1/bl1/bltalwm_11
    -------------------------------------------------  ---------------------------
    Total                                      8.909ns (2.265ns logic, 6.644ns route)
                                                       (25.4% logic, 74.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_7 (SLICE_X44Y27.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.940ns (data path)
  Source:               cpu_data<7> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.940ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<7> to AGNUS1/bl1/bltalwm_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P155.I               Tiopi                 1.530   cpu_data<7>
                                                       cpu_data<7>
                                                       cpu_data_7_IOBUF/IBUF
    SLICE_X30Y19.G2      net (fanout=22)       4.663   N954
    SLICE_X30Y19.Y       Tilo                  0.486   DENISE1/hdiwstrt<2>
                                                       gary_cpu_data_in<7>1
    SLICE_X33Y18.F4      net (fanout=5)        0.290   gary_cpu_data_in<7>
    SLICE_X33Y18.X       Tilo                  0.441   AGNUS1/bl1/bltadat<7>
                                                       GARY1/custom_data_in<7>1
    SLICE_X44Y27.BX      net (fanout=84)       1.813   custom_data_in<7>
    SLICE_X44Y27.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltalwm<7>
                                                       AGNUS1/bl1/bltalwm_7
    -------------------------------------------------  ---------------------------
    Total                                      8.940ns (2.174ns logic, 6.766ns route)
                                                       (24.3% logic, 75.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_12 (SLICE_X49Y30.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.994ns (data path)
  Source:               cpu_data<12> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_12 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.994ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<12> to AGNUS1/bl1/bltalwm_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P141.I               Tiopi                 1.530   cpu_data<12>
                                                       cpu_data<12>
                                                       cpu_data_12_IOBUF/IBUF
    SLICE_X27Y17.F2      net (fanout=23)       3.587   N949
    SLICE_X27Y17.X       Tilo                  0.441   AGNUS1/bpd1/dmaena_delayed<0>
                                                       gary_cpu_data_in<12>1
    SLICE_X26Y12.F1      net (fanout=4)        0.717   gary_cpu_data_in<12>
    SLICE_X26Y12.X       Tilo                  0.486   AGNUS1/bl1/height<12>
                                                       GARY1/custom_data_in<12>1
    SLICE_X49Y30.BX      net (fanout=70)       2.516   custom_data_in<12>
    SLICE_X49Y30.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltalwm<12>
                                                       AGNUS1/bl1/bltalwm_12
    -------------------------------------------------  ---------------------------
    Total                                      8.994ns (2.174ns logic, 6.820ns route)
                                                       (24.2% logic, 75.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_14 (SLICE_X49Y35.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.178ns (data path)
  Source:               cpu_data<14> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_14 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.178ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<14> to AGNUS1/bl1/bltafwm_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P137.I               Tiopi                 1.530   cpu_data<14>
                                                       cpu_data<14>
                                                       cpu_data_14_IOBUF/IBUF
    SLICE_X27Y15.F1      net (fanout=22)       3.703   N947
    SLICE_X27Y15.X       Tilo                  0.441   DENISE1/sprm0/sps0/datla<9>
                                                       gary_cpu_data_in<14>1
    SLICE_X30Y13.F2      net (fanout=4)        1.007   gary_cpu_data_in<14>
    SLICE_X30Y13.X       Tilo                  0.486   AGNUS1/bl1/height<14>
                                                       GARY1/custom_data_in<14>1
    SLICE_X49Y35.BY      net (fanout=69)       2.248   custom_data_in<14>
    SLICE_X49Y35.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<13>
                                                       AGNUS1/bl1/bltafwm_14
    -------------------------------------------------  ---------------------------
    Total                                      9.178ns (2.220ns logic, 6.958ns route)
                                                       (24.2% logic, 75.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_5 (SLICE_X44Y31.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.467ns (data path)
  Source:               cpu_data<5> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_5 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.467ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<5> to AGNUS1/bl1/bltafwm_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P165.I               Tiopi                 1.530   cpu_data<5>
                                                       cpu_data<5>
                                                       cpu_data_5_IOBUF/IBUF
    SLICE_X34Y16.G2      net (fanout=19)       3.057   N956
    SLICE_X34Y16.Y       Tilo                  0.486   DENISE1/hpos<8>
                                                       gary_cpu_data_in<5>1
    SLICE_X35Y20.F2      net (fanout=4)        2.412   gary_cpu_data_in<5>
    SLICE_X35Y20.X       Tilo                  0.441   AGNUS1/bl1/bltadat<5>
                                                       GARY1/custom_data_in<5>1
    SLICE_X44Y31.BX      net (fanout=89)       1.824   custom_data_in<5>
    SLICE_X44Y31.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltafwm<5>
                                                       AGNUS1/bl1/bltafwm_5
    -------------------------------------------------  ---------------------------
    Total                                      9.467ns (2.174ns logic, 7.293ns route)
                                                       (23.0% logic, 77.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_15 (SLICE_X49Y36.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.513ns (data path)
  Source:               cpu_data<15> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_15 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.513ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<15> to AGNUS1/bl1/bltafwm_15
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P135.I               Tiopi                 1.530   cpu_data<15>
                                                       cpu_data<15>
                                                       cpu_data_15_IOBUF/IBUF
    SLICE_X27Y15.G1      net (fanout=27)       3.828   N946
    SLICE_X27Y15.Y       Tilo                  0.441   DENISE1/sprm0/sps0/datla<9>
                                                       gary_cpu_data_in<15>1
    SLICE_X24Y21.F1      net (fanout=5)        0.867   gary_cpu_data_in<15>
    SLICE_X24Y21.X       Tilo                  0.486   AGNUS1/bpd1/vdiwstop<7>
                                                       GARY1/custom_data_in<15>1
    SLICE_X49Y36.BY      net (fanout=131)      2.598   custom_data_in<15>
    SLICE_X49Y36.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<15>
                                                       AGNUS1/bl1/bltafwm_15
    -------------------------------------------------  ---------------------------
    Total                                      9.513ns (2.220ns logic, 7.293ns route)
                                                       (23.3% logic, 76.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_13 (SLICE_X49Y30.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.716ns (data path)
  Source:               cpu_data<13> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_13 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.716ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<13> to AGNUS1/bl1/bltalwm_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P139.I               Tiopi                 1.530   cpu_data<13>
                                                       cpu_data<13>
                                                       cpu_data_13_IOBUF/IBUF
    SLICE_X24Y14.F2      net (fanout=21)       3.929   N948
    SLICE_X24Y14.X       Tilo                  0.486   gary_cpu_data_in<13>
                                                       gary_cpu_data_in<13>1
    SLICE_X29Y12.F2      net (fanout=4)        1.379   gary_cpu_data_in<13>
    SLICE_X29Y12.X       Tilo                  0.441   AGNUS1/bl1/height<13>
                                                       GARY1/custom_data_in<13>1
    SLICE_X49Y30.BY      net (fanout=70)       2.188   custom_data_in<13>
    SLICE_X49Y30.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<12>
                                                       AGNUS1/bl1/bltalwm_13
    -------------------------------------------------  ---------------------------
    Total                                      9.716ns (2.220ns logic, 7.496ns route)
                                                       (22.8% logic, 77.2% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_3 (SLICE_X47Y28.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.764ns (data path)
  Source:               cpu_data<3> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.764ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<3> to AGNUS1/bl1/bltalwm_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P162.I               Tiopi                 1.530   cpu_data<3>
                                                       cpu_data<3>
                                                       cpu_data_3_IOBUF/IBUF
    SLICE_X32Y13.G3      net (fanout=20)       4.065   N958
    SLICE_X32Y13.Y       Tilo                  0.486   AGNUS1/bpd1/bplcon0<2>
                                                       gary_cpu_data_in<3>1
    SLICE_X28Y22.G1      net (fanout=5)        1.162   gary_cpu_data_in<3>
    SLICE_X28Y22.Y       Tilo                  0.486   AGNUS1/bl1/bltadat<3>
                                                       GARY1/custom_data_in<3>1
    SLICE_X47Y28.BY      net (fanout=93)       2.272   custom_data_in<3>
    SLICE_X47Y28.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<2>
                                                       AGNUS1/bl1/bltalwm_3
    -------------------------------------------------  ---------------------------
    Total                                      9.764ns (2.265ns logic, 7.499ns route)
                                                       (23.2% logic, 76.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_7 (SLICE_X44Y31.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.812ns (data path)
  Source:               cpu_data<7> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.812ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<7> to AGNUS1/bl1/bltafwm_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P155.I               Tiopi                 1.530   cpu_data<7>
                                                       cpu_data<7>
                                                       cpu_data_7_IOBUF/IBUF
    SLICE_X30Y19.G2      net (fanout=22)       4.663   N954
    SLICE_X30Y19.Y       Tilo                  0.486   DENISE1/hdiwstrt<2>
                                                       gary_cpu_data_in<7>1
    SLICE_X33Y18.F4      net (fanout=5)        0.290   gary_cpu_data_in<7>
    SLICE_X33Y18.X       Tilo                  0.441   AGNUS1/bl1/bltadat<7>
                                                       GARY1/custom_data_in<7>1
    SLICE_X44Y31.BY      net (fanout=84)       2.639   custom_data_in<7>
    SLICE_X44Y31.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<5>
                                                       AGNUS1/bl1/bltafwm_7
    -------------------------------------------------  ---------------------------
    Total                                      9.812ns (2.220ns logic, 7.592ns route)
                                                       (22.6% logic, 77.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_11 (SLICE_X53Y34.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.809ns (data path)
  Source:               cpu_data<11> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_11 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.809ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<11> to AGNUS1/bl1/bltafwm_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P144.I               Tiopi                 1.530   cpu_data<11>
                                                       cpu_data<11>
                                                       cpu_data_11_IOBUF/IBUF
    SLICE_X26Y15.G3      net (fanout=21)       3.030   N950
    SLICE_X26Y15.Y       Tilo                  0.486   AGNUS1/bpd1/dmaena_delayed<1>
                                                       gary_cpu_data_in<11>1
    SLICE_X28Y13.F1      net (fanout=3)        0.501   gary_cpu_data_in<11>
    SLICE_X28Y13.X       Tilo                  0.486   AGNUS1/bl1/height<11>
                                                       GARY1/custom_data_in<11>1
    SLICE_X53Y34.BX      net (fanout=72)       4.059   custom_data_in<11>
    SLICE_X53Y34.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltafwm<11>
                                                       AGNUS1/bl1/bltafwm_11
    -------------------------------------------------  ---------------------------
    Total                                      9.809ns (2.219ns logic, 7.590ns route)
                                                       (22.6% logic, 77.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_13 (SLICE_X49Y35.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.942ns (data path)
  Source:               cpu_data<13> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_13 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.942ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<13> to AGNUS1/bl1/bltafwm_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P139.I               Tiopi                 1.530   cpu_data<13>
                                                       cpu_data<13>
                                                       cpu_data_13_IOBUF/IBUF
    SLICE_X24Y14.F2      net (fanout=21)       3.929   N948
    SLICE_X24Y14.X       Tilo                  0.486   gary_cpu_data_in<13>
                                                       gary_cpu_data_in<13>1
    SLICE_X29Y12.F2      net (fanout=4)        1.379   gary_cpu_data_in<13>
    SLICE_X29Y12.X       Tilo                  0.441   AGNUS1/bl1/height<13>
                                                       GARY1/custom_data_in<13>1
    SLICE_X49Y35.BX      net (fanout=70)       2.460   custom_data_in<13>
    SLICE_X49Y35.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltafwm<13>
                                                       AGNUS1/bl1/bltafwm_13
    -------------------------------------------------  ---------------------------
    Total                                      9.942ns (2.174ns logic, 7.768ns route)
                                                       (21.9% logic, 78.1% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_12 (SLICE_X53Y34.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.997ns (data path)
  Source:               cpu_data<12> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_12 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.997ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<12> to AGNUS1/bl1/bltafwm_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P141.I               Tiopi                 1.530   cpu_data<12>
                                                       cpu_data<12>
                                                       cpu_data_12_IOBUF/IBUF
    SLICE_X27Y17.F2      net (fanout=23)       3.587   N949
    SLICE_X27Y17.X       Tilo                  0.441   AGNUS1/bpd1/dmaena_delayed<0>
                                                       gary_cpu_data_in<12>1
    SLICE_X26Y12.F1      net (fanout=4)        0.717   gary_cpu_data_in<12>
    SLICE_X26Y12.X       Tilo                  0.486   AGNUS1/bl1/height<12>
                                                       GARY1/custom_data_in<12>1
    SLICE_X53Y34.BY      net (fanout=70)       3.473   custom_data_in<12>
    SLICE_X53Y34.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<11>
                                                       AGNUS1/bl1/bltafwm_12
    -------------------------------------------------  ---------------------------
    Total                                      9.997ns (2.220ns logic, 7.777ns route)
                                                       (22.2% logic, 77.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_3 (SLICE_X47Y33.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.990ns (data path)
  Source:               cpu_data<3> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.990ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<3> to AGNUS1/bl1/bltafwm_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P162.I               Tiopi                 1.530   cpu_data<3>
                                                       cpu_data<3>
                                                       cpu_data_3_IOBUF/IBUF
    SLICE_X32Y13.G3      net (fanout=20)       4.065   N958
    SLICE_X32Y13.Y       Tilo                  0.486   AGNUS1/bpd1/bplcon0<2>
                                                       gary_cpu_data_in<3>1
    SLICE_X28Y22.G1      net (fanout=5)        1.162   gary_cpu_data_in<3>
    SLICE_X28Y22.Y       Tilo                  0.486   AGNUS1/bl1/bltadat<3>
                                                       GARY1/custom_data_in<3>1
    SLICE_X47Y33.BX      net (fanout=93)       2.544   custom_data_in<3>
    SLICE_X47Y33.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltafwm<3>
                                                       AGNUS1/bl1/bltafwm_3
    -------------------------------------------------  ---------------------------
    Total                                      9.990ns (2.219ns logic, 7.771ns route)
                                                       (22.2% logic, 77.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_5 (SLICE_X45Y25.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      10.214ns (data path)
  Source:               cpu_data<5> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_5 (FF)
  Requirement:          0.000ns
  Data Path Delay:      10.214ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<5> to AGNUS1/bl1/bltalwm_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P165.I               Tiopi                 1.530   cpu_data<5>
                                                       cpu_data<5>
                                                       cpu_data_5_IOBUF/IBUF
    SLICE_X34Y16.G2      net (fanout=19)       3.057   N956
    SLICE_X34Y16.Y       Tilo                  0.486   DENISE1/hpos<8>
                                                       gary_cpu_data_in<5>1
    SLICE_X35Y20.F2      net (fanout=4)        2.412   gary_cpu_data_in<5>
    SLICE_X35Y20.X       Tilo                  0.441   AGNUS1/bl1/bltadat<5>
                                                       GARY1/custom_data_in<5>1
    SLICE_X45Y25.BX      net (fanout=89)       2.571   custom_data_in<5>
    SLICE_X45Y25.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltalwm<5>
                                                       AGNUS1/bl1/bltalwm_5
    -------------------------------------------------  ---------------------------
    Total                                     10.214ns (2.174ns logic, 8.040ns route)
                                                       (21.3% logic, 78.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_4 (SLICE_X46Y31.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      10.389ns (data path)
  Source:               cpu_data<4> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      10.389ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<4> to AGNUS1/bl1/bltalwm_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P166.I               Tiopi                 1.530   cpu_data<4>
                                                       cpu_data<4>
                                                       cpu_data_4_IOBUF/IBUF
    SLICE_X33Y14.F2      net (fanout=19)       3.472   N957
    SLICE_X33Y14.X       Tilo                  0.441   DENISE1/sprm0/sps3/hstart<6>
                                                       gary_cpu_data_in<4>1
    SLICE_X35Y10.G1      net (fanout=6)        2.375   gary_cpu_data_in<4>
    SLICE_X35Y10.Y       Tilo                  0.441   AGNUS1/bl1/bltadat<4>
                                                       GARY1/custom_data_in<4>1
    SLICE_X46Y31.BY      net (fanout=93)       2.367   custom_data_in<4>
    SLICE_X46Y31.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<4>
                                                       AGNUS1/bl1/bltalwm_4
    -------------------------------------------------  ---------------------------
    Total                                     10.389ns (2.175ns logic, 8.214ns route)
                                                       (20.9% logic, 79.1% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_8 (SLICE_X42Y29.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      10.422ns (data path)
  Source:               cpu_data<8> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      10.422ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<8> to AGNUS1/bl1/bltalwm_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P152.I               Tiopi                 1.530   cpu_data<8>
                                                       cpu_data<8>
                                                       cpu_data_8_IOBUF/IBUF
    SLICE_X27Y10.G2      net (fanout=22)       4.680   N953
    SLICE_X27Y10.Y       Tilo                  0.441   _l_data_14
                                                       gary_cpu_data_in<8>1
    SLICE_X29Y18.F2      net (fanout=3)        1.716   gary_cpu_data_in<8>
    SLICE_X29Y18.X       Tilo                  0.441   AGNUS1/bl1/bltadat<8>
                                                       GARY1/custom_data_in<8>1
    SLICE_X42Y29.BY      net (fanout=72)       1.851   custom_data_in<8>
    SLICE_X42Y29.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<8>
                                                       AGNUS1/bl1/bltalwm_8
    -------------------------------------------------  ---------------------------
    Total                                     10.422ns (2.175ns logic, 8.247ns route)
                                                       (20.9% logic, 79.1% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_8 (SLICE_X42Y33.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      10.696ns (data path)
  Source:               cpu_data<8> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      10.696ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<8> to AGNUS1/bl1/bltafwm_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P152.I               Tiopi                 1.530   cpu_data<8>
                                                       cpu_data<8>
                                                       cpu_data_8_IOBUF/IBUF
    SLICE_X27Y10.G2      net (fanout=22)       4.680   N953
    SLICE_X27Y10.Y       Tilo                  0.441   _l_data_14
                                                       gary_cpu_data_in<8>1
    SLICE_X29Y18.F2      net (fanout=3)        1.716   gary_cpu_data_in<8>
    SLICE_X29Y18.X       Tilo                  0.441   AGNUS1/bl1/bltadat<8>
                                                       GARY1/custom_data_in<8>1
    SLICE_X42Y33.BY      net (fanout=72)       2.125   custom_data_in<8>
    SLICE_X42Y33.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<8>
                                                       AGNUS1/bl1/bltafwm_8
    -------------------------------------------------  ---------------------------
    Total                                     10.696ns (2.175ns logic, 8.521ns route)
                                                       (20.3% logic, 79.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_10 (SLICE_X49Y33.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      10.822ns (data path)
  Source:               cpu_data<10> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_10 (FF)
  Requirement:          0.000ns
  Data Path Delay:      10.822ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<10> to AGNUS1/bl1/bltafwm_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P147.I               Tiopi                 1.530   cpu_data<10>
                                                       cpu_data<10>
                                                       cpu_data_10_IOBUF/IBUF
    SLICE_X26Y15.F3      net (fanout=22)       3.931   N951
    SLICE_X26Y15.X       Tilo                  0.486   AGNUS1/bpd1/dmaena_delayed<1>
                                                       gary_cpu_data_in<10>1
    SLICE_X30Y6.F2       net (fanout=3)        1.246   gary_cpu_data_in<10>
    SLICE_X30Y6.X        Tilo                  0.486   AGNUS1/bl1/height<10>
                                                       GARY1/custom_data_in<10>1
    SLICE_X49Y33.BY      net (fanout=75)       3.380   custom_data_in<10>
    SLICE_X49Y33.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<10>
                                                       AGNUS1/bl1/bltafwm_10
    -------------------------------------------------  ---------------------------
    Total                                     10.822ns (2.265ns logic, 8.557ns route)
                                                       (20.9% logic, 79.1% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_10 (SLICE_X48Y31.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      10.941ns (data path)
  Source:               cpu_data<10> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_10 (FF)
  Requirement:          0.000ns
  Data Path Delay:      10.941ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<10> to AGNUS1/bl1/bltalwm_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P147.I               Tiopi                 1.530   cpu_data<10>
                                                       cpu_data<10>
                                                       cpu_data_10_IOBUF/IBUF
    SLICE_X26Y15.F3      net (fanout=22)       3.931   N951
    SLICE_X26Y15.X       Tilo                  0.486   AGNUS1/bpd1/dmaena_delayed<1>
                                                       gary_cpu_data_in<10>1
    SLICE_X30Y6.F2       net (fanout=3)        1.246   gary_cpu_data_in<10>
    SLICE_X30Y6.X        Tilo                  0.486   AGNUS1/bl1/height<10>
                                                       GARY1/custom_data_in<10>1
    SLICE_X48Y31.BX      net (fanout=75)       3.545   custom_data_in<10>
    SLICE_X48Y31.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltalwm<10>
                                                       AGNUS1/bl1/bltalwm_10
    -------------------------------------------------  ---------------------------
    Total                                     10.941ns (2.219ns logic, 8.722ns route)
                                                       (20.3% logic, 79.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_4 (SLICE_X47Y33.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      11.251ns (data path)
  Source:               cpu_data<4> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      11.251ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<4> to AGNUS1/bl1/bltafwm_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P166.I               Tiopi                 1.530   cpu_data<4>
                                                       cpu_data<4>
                                                       cpu_data_4_IOBUF/IBUF
    SLICE_X33Y14.F2      net (fanout=19)       3.472   N957
    SLICE_X33Y14.X       Tilo                  0.441   DENISE1/sprm0/sps3/hstart<6>
                                                       gary_cpu_data_in<4>1
    SLICE_X35Y10.G1      net (fanout=6)        2.375   gary_cpu_data_in<4>
    SLICE_X35Y10.Y       Tilo                  0.441   AGNUS1/bl1/bltadat<4>
                                                       GARY1/custom_data_in<4>1
    SLICE_X47Y33.BY      net (fanout=93)       3.229   custom_data_in<4>
    SLICE_X47Y33.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<3>
                                                       AGNUS1/bl1/bltafwm_4
    -------------------------------------------------  ---------------------------
    Total                                     11.251ns (2.175ns logic, 9.076ns route)
                                                       (19.3% logic, 80.7% route)

--------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_chip28
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_chip28                      |     35.242ns|     30.068ns|     29.465ns|            0|            0|      1807016|    154406524|
| TS_chip7                      |    140.968ns|    117.860ns|          N/A|            0|            0|    154406524|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.


Timing summary:
---------------

Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)

Constraints cover 156215758 paths, 0 nets, and 26505 connections

Design statistics:
   Minimum period: 117.860ns{1}   (Maximum frequency:   8.485MHz)
   Maximum path delay from/to any node:  14.758ns


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Thu Sep 17 17:27:21 2026 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 419 MB



