TS11 maximum
21.631ns (requirement - data path)
  Source:               RAM1/_ce_2 (FF)
  Destination:          _ram_ce<2> (PAD)
  Requirement:          33.000ns
  Data Path Delay:      11.369ns (Levels of Logic = 1)
  Source Clock:         clk28m rising at 0.000ns

  Maximum Data Path: RAM1/_ce_2 to _ram_ce<2>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y26.XQ      Tcko                  0.720   _ce_2
                                                       RAM1/_ce_2
    P15.O1               net (fanout=1)        3.643   _ce_2
    P15.PAD              Tioop                 7.006   _ram_ce<2>
                                                       &ram_ce_2_OBUF
                                                       _ram_ce<2>
    -------------------------------------------------  ---------------------------
    Total                                     11.369ns (7.726ns logic, 3.643ns route)
                                                       (68.0% logic, 32.0% route)

TS11 minimum
8.267ns (data path)
  Source:               RAM1/_oe (FF)
  Destination:          _ram_oe (PAD)
  Requirement:          0.000ns
  Data Path Delay:      8.267ns (Levels of Logic = 1)

  Minimum Data Path: RAM1/_oe to _ram_oe
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X0Y26.YQ       Tcko                  0.576   _oe
                                                       RAM1/_oe
    P39.O1               net (fanout=1)        0.977   _oe
    P39.PAD              Tioop                 6.714   _ram_oe
                                                       &ram_oe_OBUF
                                                       _ram_oe
    -------------------------------------------------  ---------------------------
    Total                                      8.267ns (7.290ns logic, 0.977ns route)
                                                       (88.2% logic, 11.8% route)

TS20 maximum
20.783ns (requirement - data path)
  Source:               cpu_data<7> (PAD)
  Destination:          RAM1/write_data_7 (FF)
  Requirement:          33.000ns
  Data Path Delay:      12.217ns (Levels of Logic = 3)
  Destination Clock:    clk28m rising at 0.000ns

  Maximum Data Path: cpu_data<7> to RAM1/write_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P155.I               Tiopi                 1.918   cpu_data<7>
                                                       cpu_data<7>
                                                       cpu_data_7_IOBUF/IBUF
    SLICE_X30Y19.G2      net (fanout=22)       5.828   N954
    SLICE_X30Y19.Y       Tilo                  0.608   DENISE1/hdiwstrt<2>
                                                       gary_cpu_data_in<7>1
    SLICE_X33Y23.F2      net (fanout=5)        3.230   gary_cpu_data_in<7>
    SLICE_X33Y23.CLK     Tfck                  0.633   write_data_7
                                                       GARY1/ram_data_in<7>
                                                       RAM1/write_data_7
    -------------------------------------------------  ---------------------------
    Total                                     12.217ns (3.159ns logic, 9.058ns route)
                                                       (25.9% logic, 74.1% route)

TS20 minimum
5.449ns (data path)
  Source:               cpu_data<11> (PAD)
  Destination:          RAM1/write_data_11 (FF)
  Requirement:          0.000ns
  Data Path Delay:      5.449ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<11> to RAM1/write_data_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P144.I               Tiopi                 1.530   cpu_data<11>
                                                       cpu_data<11>
                                                       cpu_data_11_IOBUF/IBUF
    SLICE_X26Y15.G3      net (fanout=21)       3.030   N950
    SLICE_X26Y15.Y       Tilo                  0.486   AGNUS1/bpd1/dmaena_delayed<1>
                                                       gary_cpu_data_in<11>1
    SLICE_X26Y17.F3      net (fanout=3)        0.297   gary_cpu_data_in<11>
    SLICE_X26Y17.CLK     Tckf        (-Th)    -0.106   write_data_11
                                                       GARY1/ram_data_in<11>
                                                       RAM1/write_data_11
    -------------------------------------------------  ---------------------------
    Total                                      5.449ns (2.122ns logic, 3.327ns route)
                                                       (38.9% logic, 61.1% route)

TS21 maximum
3.003ns (requirement - data path)
  Source:               CPU1/cache_data_selected (FF)
  Destination:          cpu_data<6> (PAD)
  Requirement:          16.000ns
  Data Path Delay:      12.997ns (Levels of Logic = 2)
  Source Clock:         cpu_clk_OBUF falling at 8.292ns

  Maximum Data Path: CPU1/cache_data_selected to cpu_data<6>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X51Y33.XQ      Tcko                  0.720   CPU1/cache_data_selected
                                                       CPU1/cache_data_selected
    SLICE_X52Y23.F3      net (fanout=19)       1.757   CPU1/cache_data_selected
    SLICE_X52Y23.X       Tilo                  0.608   CPU1/cache_data_held<6>
                                                       CPU1/data_mux0000<6>1
    P161.O1              net (fanout=1)        2.906   cpu_data_6_IOBUF
    P161.PAD             Tioop                 7.006   cpu_data<6>
                                                       cpu_data_6_IOBUF/OBUFT
                                                       cpu_data<6>
    -------------------------------------------------  ---------------------------
    Total                                     12.997ns (8.334ns logic, 4.663ns route)
                                                       (64.1% logic, 35.9% route)

TS21 minimum
9.528ns (data path)
  Source:               CPU1/cache_data_selected (FF)
  Destination:          cpu_data<11> (PAD)
  Requirement:          0.000ns
  Data Path Delay:      9.528ns (Levels of Logic = 2)

  Minimum Data Path: CPU1/cache_data_selected to cpu_data<11>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X51Y33.XQ      Tcko                  0.576   CPU1/cache_data_selected
                                                       CPU1/cache_data_selected
    SLICE_X50Y33.F3      net (fanout=19)       0.402   CPU1/cache_data_selected
    SLICE_X50Y33.X       Tilo                  0.486   CPU1/cache_lookup_hit
                                                       CPU1/data_mux0000<11>1
    P144.O1              net (fanout=1)        1.350   cpu_data_11_IOBUF
    P144.PAD             Tioop                 6.714   cpu_data<11>
                                                       cpu_data_11_IOBUF/OBUFT
                                                       cpu_data<11>
    -------------------------------------------------  ---------------------------
    Total                                      9.528ns (7.776ns logic, 1.752ns route)
                                                       (81.6% logic, 18.4% route)

TS22 maximum
0.095ns (requirement - data path)
  Source:               CPU1/_ta_t (FF)
  Destination:          _cpu_dtack (PAD)
  Requirement:          5.750ns
  Data Path Delay:      5.655ns (Levels of Logic = 3)
  Source Clock:         cpu_clk_OBUF rising at 0.000ns

  Maximum Data Path: CPU1/_ta_t to _cpu_dtack
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X45Y40.YQ      Tcko                  0.720   CPU1/_ta_t
                                                       CPU1/_ta_t
    SLICE_X45Y41.F4      net (fanout=3)        0.498   CPU1/_ta_t
    SLICE_X45Y41.X       Tilo                  0.551   PAULA1/rxint
                                                       CPU1/cpu_write_wait1
    SLICE_X55Y42.G3      net (fanout=1)        0.973   CPU1/cpu_write_wait
    SLICE_X55Y42.Y       Tilo                  0.551   &cpu_dtack_OBUF
                                                       CPU1/_dtack1
    P138.O1              net (fanout=1)        0.720   &cpu_dtack_OBUF
    P138.PAD             Tioop                 1.642   _cpu_dtack
                                                       &cpu_dtack_OBUF
                                                       _cpu_dtack
    -------------------------------------------------  ---------------------------
    Total                                      5.655ns (3.464ns logic, 2.191ns route)
                                                       (61.3% logic, 38.7% route)

TS22 minimum
4.326ns (data path)
  Source:               CPU1/read_ack (FF)
  Destination:          _cpu_dtack (PAD)
  Requirement:          0.000ns
  Data Path Delay:      4.326ns (Levels of Logic = 3)

  Minimum Data Path: CPU1/read_ack to _cpu_dtack
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X53Y42.YQ      Tcko                  0.576   CPU1/read_ack
                                                       CPU1/read_ack
    SLICE_X52Y42.F3      net (fanout=1)        0.358   CPU1/read_ack
    SLICE_X52Y42.X       Tilo                  0.486   PAULA1/pu1/txdiv<10>
                                                       CPU1/cpu_read_wait1
    SLICE_X55Y42.G1      net (fanout=1)        0.539   CPU1/cpu_read_wait
    SLICE_X55Y42.Y       Tilo                  0.441   &cpu_dtack_OBUF
                                                       CPU1/_dtack1
    P138.O1              net (fanout=1)        0.576   &cpu_dtack_OBUF
    P138.PAD             Tioop                 1.350   _cpu_dtack
                                                       &cpu_dtack_OBUF
                                                       _cpu_dtack
    -------------------------------------------------  ---------------------------
    Total                                      4.326ns (2.853ns logic, 1.473ns route)
                                                       (66.0% logic, 34.0% route)

TS23 maximum
11.746ns (requirement - data path)
  Source:               _cpu_lds (PAD)
  Destination:          CPU1/cache_lookup_hit (FF)
  Requirement:          20.000ns
  Data Path Delay:      8.254ns (Levels of Logic = 3)
  Destination Clock:    cpu_clk_OBUF falling at 8.292ns

  Maximum Data Path: _cpu_lds to CPU1/cache_lookup_hit
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P143.I               Tiopi                 1.918   _cpu_lds
                                                       _cpu_lds
                                                       &cpu_lds_IBUF
    SLICE_X54Y21.F4      net (fanout=5)        3.463   &cpu_lds_IBUF
    SLICE_X54Y21.X       Tilo                  0.608   DENISE1/sprm0/sps3/datlb<0>
                                                       CPU1/cache_lookup_hit_and0000_SW0
    SLICE_X50Y33.G1      net (fanout=1)        1.575   CPU1/N161
    SLICE_X50Y33.CLK     Tgck                  0.690   CPU1/cache_lookup_hit
                                                       CPU1/cache_lookup_hit_and0000
                                                       CPU1/cache_lookup_hit
    -------------------------------------------------  ---------------------------
    Total                                      8.254ns (3.216ns logic, 5.038ns route)
                                                       (39.0% logic, 61.0% route)

TS23 minimum
4.851ns (data path)
  Source:               _cpu_uds (PAD)
  Destination:          CPU1/cache_lookup_hit (FF)
  Requirement:          0.000ns
  Data Path Delay:      4.851ns (Levels of Logic = 3)

  Minimum Data Path: _cpu_uds to CPU1/cache_lookup_hit
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P146.I               Tiopi                 1.530   _cpu_uds
                                                       _cpu_uds
                                                       &cpu_uds_IBUF
    SLICE_X54Y21.F3      net (fanout=5)        1.469   &cpu_uds_IBUF
    SLICE_X54Y21.X       Tilo                  0.486   DENISE1/sprm0/sps3/datlb<0>
                                                       CPU1/cache_lookup_hit_and0000_SW0
    SLICE_X50Y33.G1      net (fanout=1)        1.260   CPU1/N161
    SLICE_X50Y33.CLK     Tckg        (-Th)    -0.106   CPU1/cache_lookup_hit
                                                       CPU1/cache_lookup_hit_and0000
                                                       CPU1/cache_lookup_hit
    -------------------------------------------------  ---------------------------
    Total                                      4.851ns (2.122ns logic, 2.729ns route)
                                                       (43.7% logic, 56.3% route)

TS24 maximum
1.886ns (requirement - data path)
  Source:               CPU1/read_data_held_6 (FF)
  Destination:          cpu_data<6> (PAD)
  Requirement:          16.000ns
  Data Path Delay:      14.114ns (Levels of Logic = 2)
  Source Clock:         clk rising at 0.000ns

  Maximum Data Path: CPU1/read_data_held_6 to cpu_data<6>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X39Y32.XQ      Tcko                  0.720   CPU1/read_data_held<6>
                                                       CPU1/read_data_held_6
    SLICE_X52Y23.F1      net (fanout=2)        2.874   CPU1/read_data_held<6>
    SLICE_X52Y23.X       Tilo                  0.608   CPU1/cache_data_held<6>
                                                       CPU1/data_mux0000<6>1
    P161.O1              net (fanout=1)        2.906   cpu_data_6_IOBUF
    P161.PAD             Tioop                 7.006   cpu_data<6>
                                                       cpu_data_6_IOBUF/OBUFT
                                                       cpu_data<6>
    -------------------------------------------------  ---------------------------
    Total                                     14.114ns (8.334ns logic, 5.780ns route)
                                                       (59.0% logic, 41.0% route)

TS24 minimum
10.030ns (data path)
  Source:               CPU1/read_data_held_4 (FF)
  Destination:          cpu_data<4> (PAD)
  Requirement:          0.000ns
  Data Path Delay:      10.030ns (Levels of Logic = 2)

  Minimum Data Path: CPU1/read_data_held_4 to cpu_data<4>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X41Y27.XQ      Tcko                  0.576   CPU1/read_data_held<4>
                                                       CPU1/read_data_held_4
    SLICE_X48Y26.G3      net (fanout=2)        0.866   CPU1/read_data_held<4>
    SLICE_X48Y26.Y       Tilo                  0.486   CPU1/cache_data_held<1>
                                                       CPU1/data_mux0000<4>1
    P166.O1              net (fanout=1)        1.388   cpu_data_4_IOBUF
    P166.PAD             Tioop                 6.714   cpu_data<4>
                                                       cpu_data_4_IOBUF/OBUFT
                                                       cpu_data<4>
    -------------------------------------------------  ---------------------------
    Total                                     10.030ns (7.776ns logic, 2.254ns route)
                                                       (77.5% logic, 22.5% route)

TS25 maximum
9.280ns (requirement - (data path - clock path skew + uncertainty))
  Source:               CPU1/read_data_held_9 (FF)
  Destination:          CPU1/Mram_cache_data_hi.A (RAM)
  Requirement:          16.000ns
  Data Path Delay:      6.720ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising
  Destination Clock:    cpu_clk_OBUF falling
  Clock Uncertainty:    0.000ns

  Maximum Data Path: CPU1/read_data_held_9 to CPU1/Mram_cache_data_hi.A
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X35Y33.XQ      Tcko                  0.720   CPU1/read_data_held<9>
                                                       CPU1/read_data_held_9
    SLICE_X51Y31.G3      net (fanout=2)        2.016   CPU1/read_data_held<9>
    SLICE_X51Y31.Y       Tilo                  0.551   AGNUS1/bl1/bltcdat<15>
                                                       CPU1/cache_input_hi<1>1
    RAMB16_X1Y0.DIA1     net (fanout=1)        2.949   CPU1/cache_input_hi<1>
    RAMB16_X1Y0.CLKA     Tbdck                 0.484   CPU1/Mram_cache_data_hi
                                                       CPU1/Mram_cache_data_hi.A
    -------------------------------------------------  ---------------------------
    Total                                      6.720ns (1.755ns logic, 4.965ns route)
                                                       (26.1% logic, 73.9% route)

TS25 minimum
3.341ns (requirement - (clock path skew + uncertainty - data path))
  Source:               CPU1/read_data_held_3 (FF)
  Destination:          CPU1/Mram_cache_data_lo.A (RAM)
  Requirement:          0.000ns
  Data Path Delay:      3.341ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising
  Destination Clock:    cpu_clk_OBUF falling
  Clock Uncertainty:    0.000ns

  Minimum Data Path: CPU1/read_data_held_3 to CPU1/Mram_cache_data_lo.A
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X38Y28.XQ      Tcko                  0.576   CPU1/read_data_held<3>
                                                       CPU1/read_data_held_3
    SLICE_X50Y27.G3      net (fanout=2)        1.237   CPU1/read_data_held<3>
    SLICE_X50Y27.Y       Tilo                  0.486   CPU1/cache_input_lo<0>
                                                       CPU1/cache_input_lo<3>1
    RAMB16_X1Y1.DIA3     net (fanout=1)        1.042   CPU1/cache_input_lo<3>
    RAMB16_X1Y1.CLKA     Tbckd       (-Th)     0.000   CPU1/Mram_cache_data_lo
                                                       CPU1/Mram_cache_data_lo.A
    -------------------------------------------------  ---------------------------
    Total                                      3.341ns (1.062ns logic, 2.279ns route)
                                                       (31.8% logic, 68.2% route)

TS_AUDIT_SRAM_DOE_HOLD maximum
20.786ns (requirement - data path)
  Source:               RAM1/doe_hold (FF)
  Destination:          ram_data<7> (PAD)
  Requirement:          33.000ns
  Data Path Delay:      12.214ns (Levels of Logic = 2)
  Source Clock:         clk28m falling at 17.621ns

  Maximum Data Path: RAM1/doe_hold to ram_data<7>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X5Y12.YQ       Tcko                  0.720   RAM1/doe_hold
                                                       RAM1/doe_hold
    SLICE_X7Y14.F1       net (fanout=1)        0.560   RAM1/doe_hold
    SLICE_X7Y14.X        Tilo                  0.551   AGNUS1/cp1/copjmp2
                                                       RAM1/data_or0000_inv1
    P71.T1               net (fanout=16)       3.135   data_or0000_inv
    P71.PAD              Tiotp                 7.248   ram_data<7>
                                                       ram_data_7_IOBUF/OBUFT
                                                       ram_data<7>
    -------------------------------------------------  ---------------------------
    Total                                     12.214ns (8.519ns logic, 3.695ns route)
                                                       (69.7% logic, 30.3% route)

TS_AUDIT_SRAM_DOE_HOLD minimum
9.633ns (data path)
  Source:               RAM1/doe_hold (FF)
  Destination:          ram_data<13> (PAD)
  Requirement:          0.000ns
  Data Path Delay:      9.633ns (Levels of Logic = 2)

  Minimum Data Path: RAM1/doe_hold to ram_data<13>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X5Y12.YQ       Tcko                  0.576   RAM1/doe_hold
                                                       RAM1/doe_hold
    SLICE_X7Y14.F1       net (fanout=1)        0.448   RAM1/doe_hold
    SLICE_X7Y14.X        Tilo                  0.441   AGNUS1/cp1/copjmp2
                                                       RAM1/data_or0000_inv1
    P45.T1               net (fanout=16)       1.260   data_or0000_inv
    P45.PAD              Tiotp                 6.908   ram_data<13>
                                                       ram_data_13_IOBUF/OBUFT
                                                       ram_data<13>
    -------------------------------------------------  ---------------------------
    Total                                      9.633ns (7.925ns logic, 1.708ns route)
                                                       (82.3% logic, 17.7% route)

TS_AUDIT_SRAM_WRITE_DATA maximum
21.422ns (requirement - data path)
  Source:               RAM1/write_data_8 (FF)
  Destination:          ram_data<8> (PAD)
  Requirement:          33.000ns
  Data Path Delay:      11.578ns (Levels of Logic = 1)
  Source Clock:         clk28m rising at 0.000ns

  Maximum Data Path: RAM1/write_data_8 to ram_data<8>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X30Y21.XQ      Tcko                  0.720   write_data_8
                                                       RAM1/write_data_8
    P52.O1               net (fanout=1)        3.852   write_data_8
    P52.PAD              Tioop                 7.006   ram_data<8>
                                                       ram_data_8_IOBUF/OBUFT
                                                       ram_data<8>
    -------------------------------------------------  ---------------------------
    Total                                     11.578ns (7.726ns logic, 3.852ns route)
                                                       (66.7% logic, 33.3% route)

TS_AUDIT_SRAM_WRITE_DATA minimum
8.864ns (data path)
  Source:               RAM1/write_data_4 (FF)
  Destination:          ram_data<4> (PAD)
  Requirement:          0.000ns
  Data Path Delay:      8.864ns (Levels of Logic = 1)

  Minimum Data Path: RAM1/write_data_4 to ram_data<4>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X33Y17.XQ      Tcko                  0.576   write_data_4
                                                       RAM1/write_data_4
    P65.O1               net (fanout=1)        1.574   write_data_4
    P65.PAD              Tioop                 6.714   ram_data<4>
                                                       ram_data_4_IOBUF/OBUFT
                                                       ram_data<4>
    -------------------------------------------------  ---------------------------
    Total                                      8.864ns (7.290ns logic, 1.574ns route)
                                                       (82.2% logic, 17.8% route)

TS_AUDIT_SRAM_RAM_CAPTURE maximum
16.060ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/bpd1/Mram_bplpth5.SLICEM_F (RAM)
  Destination:          RAM1/write_data_10 (FF)
  Requirement:          35.242ns
  Data Path Delay:      18.812ns (Levels of Logic = 8)
  Clock Path Skew:      -0.016ns (1.842 - 1.858)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk28m rising at 35.242ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/bpd1/Mram_bplpth5.SLICEM_F to RAM1/write_data_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y11.X       Tshcko                1.784   AGNUS1/address_bpl<20>
                                                       AGNUS1/bpd1/Mram_bplpth5.WE
                                                       AGNUS1/bpd1/Mram_bplpth5.SLICEM_F
    SLICE_X13Y11.F3      net (fanout=2)        0.898   AGNUS1/address_bpl<20>
    SLICE_X13Y11.X       Tif5x                 0.911   MIA1/profile_sample<0>
                                                       AGNUS1/address_out<20>11_G
                                                       AGNUS1/address_out<20>11
    SLICE_X18Y12.F2      net (fanout=1)        1.524   AGNUS1/address_out<20>11
    SLICE_X18Y12.X       Tilo                  0.608   dma_address_out<20>
                                                       AGNUS1/address_out<20>54
    SLICE_X16Y24.G4      net (fanout=5)        2.522   dma_address_out<20>
    SLICE_X16Y24.Y       Tilo                  0.608   USERIO1/osd1/spi0/first_byte
                                                       GARY1/sel_slow_0_mux000016
    SLICE_X16Y24.F4      net (fanout=1)        0.015   GARY1/sel_slow_0_mux000016/O
    SLICE_X16Y24.X       Tilo                  0.608   USERIO1/osd1/spi0/first_byte
                                                       GARY1/sel_chip_1_mux00001
    SLICE_X17Y24.F4      net (fanout=4)        0.041   sel_chip<1>
    SLICE_X17Y24.X       Tilo                  0.551   USERIO1/osd1/wrdat<3>
                                                       memory_config<0>1
    SLICE_X17Y25.F2      net (fanout=1)        0.209   memory_config<0>1
    SLICE_X17Y25.X       Tif5x                 0.911   USERIO1/osd1/t_memory_config<2>
                                                       BMAP1/Mmux_bank_3
                                                       BMAP1/Mmux_bank_2_f5
    SLICE_X12Y24.G2      net (fanout=3)        0.999   bank<1>
    SLICE_X12Y24.Y       Tilo                  0.608   AGNUS1/bpd1/vdiwstrt<8>
                                                       RAM1/enable81
    SLICE_X23Y20.F1      net (fanout=25)       1.466   enable_0
    SLICE_X23Y20.X       Tilo                  0.551   RAM1/write_data_and0000
                                                       RAM1/write_data_and00001
    SLICE_X26Y16.CE      net (fanout=16)       3.396   RAM1/write_data_and0000
    SLICE_X26Y16.CLK     Tceck                 0.602   write_data_10
                                                       RAM1/write_data_10
    -------------------------------------------------  ---------------------------
    Total                                     18.812ns (7.742ns logic, 11.070ns route)
                                                       (41.2% logic, 58.8% route)

TS_AUDIT_SRAM_RAM_CAPTURE minimum
4.089ns (requirement - (clock path skew + uncertainty - data path))
  Source:               PAULA1/pf1/db1/Mram_mem1.B (RAM)
  Destination:          RAM1/write_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      4.446ns (Levels of Logic = 2)
  Clock Path Skew:      0.003ns (1.842 - 1.839)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk28m rising at 0.000ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: PAULA1/pf1/db1/Mram_mem1.B to RAM1/write_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB16_X1Y3.DOPB0    Tbcko                 1.915   PAULA1/pf1/db1/Mram_mem1
                                                       PAULA1/pf1/db1/Mram_mem1.B
    SLICE_X30Y21.G1      net (fanout=3)        1.927   disk_dma_data<8>
    SLICE_X30Y21.Y       Tilo                  0.486   write_data_8
                                                       GARY1/ram_data_in<8>_SW0
    SLICE_X30Y21.F3      net (fanout=1)        0.012   GARY1/ram_data_in<8>_SW0/O
    SLICE_X30Y21.CLK     Tckf        (-Th)    -0.106   write_data_8
                                                       GARY1/ram_data_in<8>
                                                       RAM1/write_data_8
    -------------------------------------------------  ---------------------------
    Total                                      4.446ns (2.507ns logic, 1.939ns route)
                                                       (56.4% logic, 43.6% route)

TS_AUDIT_CPU_ADDRESS_CACHE_READ maximum
994.491ns (requirement - data path)
  Source:               cpu_address<6> (PAD)
  Destination:          CPU1/Mram_cache_data_lo.B (RAM)
  Requirement:          1000.000ns
  Data Path Delay:      5.509ns (Levels of Logic = 1)
  Destination Clock:    cpu_clk_OBUF falling at 8.292ns

  Maximum Data Path: cpu_address<6> to CPU1/Mram_cache_data_lo.B
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P97.I                Tiopi                 1.918   cpu_address<6>
                                                       cpu_address<6>
                                                       cpu_address_6_IBUF
    RAMB16_X1Y1.ADDRB8   net (fanout=5)        3.241   address<6>
    RAMB16_X1Y1.CLKB     Tback                 0.350   CPU1/Mram_cache_data_lo
                                                       CPU1/Mram_cache_data_lo.B
    -------------------------------------------------  ---------------------------
    Total                                      5.509ns (2.268ns logic, 3.241ns route)
                                                       (41.2% logic, 58.8% route)

TS_AUDIT_CPU_ADDRESS_CACHE_READ minimum
2.952ns (data path)
  Source:               cpu_address<5> (PAD)
  Destination:          CPU1/Mram_cache_data_hi.B (RAM)
  Requirement:          0.000ns
  Data Path Delay:      2.952ns (Levels of Logic = 1)

  Minimum Data Path: cpu_address<5> to CPU1/Mram_cache_data_hi.B
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P95.I                Tiopi                 1.530   cpu_address<5>
                                                       cpu_address<5>
                                                       cpu_address_5_IBUF
    RAMB16_X1Y0.ADDRB7   net (fanout=5)        1.422   address<5>
    RAMB16_X1Y0.CLKB     Tbcka       (-Th)     0.000   CPU1/Mram_cache_data_hi
                                                       CPU1/Mram_cache_data_hi.B
    -------------------------------------------------  ---------------------------
    Total                                      2.952ns (1.530ns logic, 1.422ns route)
                                                       (51.8% logic, 48.2% route)

TS_AUDIT_CPU_SRAM_READ_RETURN maximum
19.495ns (requirement - data path)
  Source:               ram_data<0> (PAD)
  Destination:          CPU1/read_data_held_0 (FF)
  Requirement:          33.000ns
  Data Path Delay:      13.505ns (Levels of Logic = 7)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: ram_data<0> to CPU1/read_data_held_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P29.I                Tiopi                 1.918   ram_data<0>
                                                       ram_data<0>
                                                       ram_data_0_IOBUF/IBUF
    SLICE_X29Y22.G4      net (fanout=1)        2.362   N945
    SLICE_X29Y22.Y       Tilo                  0.551   N1934
                                                       RAM1/data_out<0>1
    SLICE_X29Y22.F1      net (fanout=3)        0.554   ram_data_out<0>
    SLICE_X29Y22.X       Tilo                  0.551   N1934
                                                       cpu_data_in<0>273_SW1_SW0
    SLICE_X29Y33.F1      net (fanout=1)        3.648   N1934
    SLICE_X29Y33.X       Tilo                  0.551   DENISE1/bplm0/pf2h<2>
                                                       cpu_data_in<0>273_SW1
    SLICE_X31Y35.F3      net (fanout=1)        0.358   N1910
    SLICE_X31Y35.X       Tilo                  0.551   N1928
                                                       cpu_data_in<0>303_SW0
    SLICE_X38Y36.G3      net (fanout=1)        1.148   N1928
    SLICE_X38Y36.Y       Tilo                  0.608   CPU1/read_data_held<0>
                                                       cpu_data_in<0>325
    SLICE_X38Y36.F4      net (fanout=1)        0.015   cpu_data_in<0>325/O
    SLICE_X38Y36.CLK     Tfck                  0.690   CPU1/read_data_held<0>
                                                       cpu_data_in<0>349
                                                       CPU1/read_data_held_0
    -------------------------------------------------  ---------------------------
    Total                                     13.505ns (5.420ns logic, 8.085ns route)
                                                       (40.1% logic, 59.9% route)

TS_AUDIT_CPU_SRAM_READ_RETURN minimum
5.468ns (data path)
  Source:               ram_data<12> (PAD)
  Destination:          CPU1/read_data_held_12 (FF)
  Requirement:          0.000ns
  Data Path Delay:      5.468ns (Levels of Logic = 3)

  Minimum Data Path: ram_data<12> to CPU1/read_data_held_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P46.I                Tiopi                 1.530   ram_data<12>
                                                       ram_data<12>
                                                       ram_data_12_IOBUF/IBUF
    SLICE_X26Y18.F4      net (fanout=2)        1.859   N933
    SLICE_X26Y18.X       Tilo                  0.486   AGNUS1/cp1/ir1<15>
                                                       cpu_data_in<12>266
    SLICE_X34Y28.F1      net (fanout=1)        1.487   cpu_data_in<12>266
    SLICE_X34Y28.CLK     Tckf        (-Th)    -0.106   CPU1/read_data_held<12>
                                                       cpu_data_in<12>421
                                                       CPU1/read_data_held_12
    -------------------------------------------------  ---------------------------
    Total                                      5.468ns (2.122ns logic, 3.346ns route)
                                                       (38.8% logic, 61.2% route)
