TS_R7_CAPTURE_PERIOD setup
Slack (setup path):     7.112ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          CPU1/read_data_held_0 (FF)
  Requirement:          35.243ns
  Data Path Delay:      27.774ns (Levels of Logic = 16)
  Clock Path Skew:      -0.003ns (1.839 - 1.842)
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to CPU1/read_data_held_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X30Y17.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.G2      net (fanout=1)        0.841   AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.Y       Tilo                  0.551   _l_data_7
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y19.F3      net (fanout=6)        0.397   AGNUS1/N1_0
    SLICE_X29Y19.X       Tilo                  0.551   _l_data_7
                                                       AGNUS1/dma_spr1
    SLICE_X12Y13.G3      net (fanout=30)       2.644   dma_spr
    SLICE_X12Y13.Y       Tilo                  0.608   AGNUS1/sprite_1
                                                       AGNUS1/address_out<10>131
    SLICE_X13Y11.G4      net (fanout=7)        0.434   AGNUS1/N41
    SLICE_X13Y11.X       Tif5x                 0.911   MIA1/profile_sample<0>
                                                       AGNUS1/address_out<20>11_F
                                                       AGNUS1/address_out<20>11
    SLICE_X18Y12.F2      net (fanout=1)        1.524   AGNUS1/address_out<20>11
    SLICE_X18Y12.X       Tilo                  0.608   dma_address_out<20>
                                                       AGNUS1/address_out<20>54
    SLICE_X16Y24.G4      net (fanout=5)        2.522   dma_address_out<20>
    SLICE_X16Y24.Y       Tilo                  0.608   USERIO1/osd1/spi0/first_byte
                                                       GARY1/sel_slow_0_mux000016
    SLICE_X16Y24.F4      net (fanout=1)        0.015   GARY1/sel_slow_0_mux000016/O
    SLICE_X16Y24.X       Tilo                  0.608   USERIO1/osd1/spi0/first_byte
                                                       GARY1/sel_chip_1_mux00001
    SLICE_X17Y24.F4      net (fanout=4)        0.041   sel_chip<1>
    SLICE_X17Y24.X       Tilo                  0.551   USERIO1/osd1/wrdat<3>
                                                       memory_config<0>1
    SLICE_X17Y25.F2      net (fanout=1)        0.209   memory_config<0>1
    SLICE_X17Y25.X       Tif5x                 0.911   USERIO1/osd1/t_memory_config<2>
                                                       BMAP1/Mmux_bank_3
                                                       BMAP1/Mmux_bank_2_f5
    SLICE_X12Y24.G2      net (fanout=3)        0.999   bank<1>
    SLICE_X12Y24.Y       Tilo                  0.608   AGNUS1/bpd1/vdiwstrt<8>
                                                       RAM1/enable81
    SLICE_X29Y22.G3      net (fanout=25)       1.688   enable_0
    SLICE_X29Y22.Y       Tilo                  0.551   N1934
                                                       RAM1/data_out<0>1
    SLICE_X29Y22.F1      net (fanout=3)        0.554   ram_data_out<0>
    SLICE_X29Y22.X       Tilo                  0.551   N1934
                                                       cpu_data_in<0>273_SW1_SW0
    SLICE_X29Y33.F1      net (fanout=1)        3.648   N1934
    SLICE_X29Y33.X       Tilo                  0.551   DENISE1/bplm0/pf2h<2>
                                                       cpu_data_in<0>273_SW1
    SLICE_X31Y35.F3      net (fanout=1)        0.358   N1910
    SLICE_X31Y35.X       Tilo                  0.551   N1928
                                                       cpu_data_in<0>303_SW0
    SLICE_X38Y36.G3      net (fanout=1)        1.148   N1928
    SLICE_X38Y36.Y       Tilo                  0.608   CPU1/read_data_held<0>
                                                       cpu_data_in<0>325
    SLICE_X38Y36.F4      net (fanout=1)        0.015   cpu_data_in<0>325/O
    SLICE_X38Y36.CLK     Tfck                  0.690   CPU1/read_data_held<0>
                                                       cpu_data_in<0>349
                                                       CPU1/read_data_held_0
    -------------------------------------------------  ---------------------------
    Total                                     27.774ns (10.737ns logic, 17.037ns route)
                                                       (38.7% logic, 61.3% route)

--------------------------------------------------------------------------------


TS_R7_CAPTURE_PERIOD hold
Slack (hold path):      1.354ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/dmacon_2 (FF)
  Destination:          CPU1/read_data_held_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.709ns (Levels of Logic = 2)
  Clock Path Skew:      0.001ns (0.142 - 0.141)
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/dmacon_2 to CPU1/read_data_held_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y31.YQ      Tcko                  0.576   dmacon_2
                                                       AGNUS1/dmacon_2
    SLICE_X34Y31.G2      net (fanout=2)        0.529   dmacon_2
    SLICE_X34Y31.Y       Tilo                  0.486   CPU1/read_data_held<2>
                                                       cpu_data_in<2>208
    SLICE_X34Y31.F3      net (fanout=1)        0.012   cpu_data_in<2>208/O
    SLICE_X34Y31.CLK     Tckf        (-Th)    -0.106   CPU1/read_data_held<2>
                                                       cpu_data_in<2>298
                                                       CPU1/read_data_held_2
    -------------------------------------------------  ---------------------------
    Total                                      1.709ns (1.168ns logic, 0.541ns route)
                                                       (68.3% logic, 31.7% route)

--------------------------------------------------------------------------------


TS_R7_SERVICE_PERIOD setup
Slack (setup path):     21.094ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          CPU1/read_complete (FF)
  Requirement:          35.243ns
  Data Path Delay:      13.791ns (Levels of Logic = 8)
  Clock Path Skew:      -0.004ns (1.838 - 1.842)
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to CPU1/read_complete
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X30Y17.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.G2      net (fanout=1)        0.841   AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.Y       Tilo                  0.551   _l_data_7
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y19.F3      net (fanout=6)        0.397   AGNUS1/N1_0
    SLICE_X29Y19.X       Tilo                  0.551   _l_data_7
                                                       AGNUS1/dma_spr1
    SLICE_X31Y21.F3      net (fanout=30)       0.753   dma_spr
    SLICE_X31Y21.X       Tilo                  0.551   DENISE1/hdiwstrt<0>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X30Y20.G4      net (fanout=29)       0.114   AGNUS1/N58
    SLICE_X30Y20.Y       Tilo                  0.608   DENISE1/bplm0/bpl6dat<5>
                                                       AGNUS1/dbr_and000073
    SLICE_X30Y20.F1      net (fanout=8)        0.608   AGNUS1/dbr_and0000
    SLICE_X30Y20.X       Tilo                  0.608   DENISE1/bplm0/bpl6dat<5>
                                                       AGNUS1/dbr
    SLICE_X30Y37.F1      net (fanout=38)       1.174   dbr
    SLICE_X30Y37.X       Tilo                  0.608   turbo
                                                       CPU1/enable114
    SLICE_X30Y36.G1      net (fanout=2)        0.590   CPU1/enable114
    SLICE_X30Y36.Y       Tilo                  0.608   CLOCK1/clocks_ready_pipe<0>
                                                       CPU1/enable
    SLICE_X31Y33.G3      net (fanout=7)        0.440   enable
    SLICE_X31Y33.Y       Tilo                  0.551   CLOCK1/fast_reset_pipe<0>
                                                       CPU1/rd1
    SLICE_X43Y40.CE      net (fanout=48)       2.916   cpu_rd
    SLICE_X43Y40.CLK     Tceck                 0.602   CPU1/read_complete
                                                       CPU1/read_complete
    -------------------------------------------------  ---------------------------
    Total                                     13.791ns (5.958ns logic, 7.833ns route)
                                                       (43.2% logic, 56.8% route)

--------------------------------------------------------------------------------


TS_R7_SERVICE_PERIOD hold
Slack (hold path):      1.611ns (requirement - (clock path skew + uncertainty - data path))
  Source:               CPU1/read_as_seen (FF)
  Destination:          CPU1/read_serviced (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.966ns (Levels of Logic = 1)
  Clock Path Skew:      0.001ns (0.142 - 0.141)
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: CPU1/read_as_seen to CPU1/read_serviced
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X30Y33.YQ      Tcko                  0.576   CPU1/read_as_seen
                                                       CPU1/read_as_seen
    SLICE_X31Y33.G4      net (fanout=4)        0.364   CPU1/read_as_seen
    SLICE_X31Y33.Y       Tilo                  0.441   CLOCK1/fast_reset_pipe<0>
                                                       CPU1/rd1
    SLICE_X28Y32.CE      net (fanout=48)       0.585   cpu_rd
    SLICE_X28Y32.CLK     Tckce       (-Th)     0.000   CPU1/read_serviced
                                                       CPU1/read_serviced
    -------------------------------------------------  ---------------------------
    Total                                      1.966ns (1.017ns logic, 0.949ns route)
                                                       (51.7% logic, 48.3% route)

--------------------------------------------------------------------------------

