TS_R4_COMPLETION equivalent PERIOD audit
214490 paths, 13 physical pins across four logical FFs; zero setup/hold errors.
Four destinations partitioned from chip7, with PERIOD TS_chip7 PHASE+0 HIGH50%; all other periods and SYSTEM_JITTER unchanged. Main PCF is unmodified.
Worst paths below are excerpts from completion.twr.

AGNUS1/bl1/busy: all setup
Slack (setup path):     11.382ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          AGNUS1/bl1/busy (FF)
  Requirement:          35.243ns
  Data Path Delay:      23.504ns (Levels of Logic = 13)
  Clock Path Skew:      -0.003ns (1.839 - 1.842)
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to AGNUS1/bl1/busy
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X30Y17.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.G2      net (fanout=1)        0.841   AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.Y       Tilo                  0.551   _l_data_7
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y19.F3      net (fanout=6)        0.397   AGNUS1/N1_0
    SLICE_X29Y19.X       Tilo                  0.551   _l_data_7
                                                       AGNUS1/dma_spr1
    SLICE_X31Y21.F3      net (fanout=30)       0.753   dma_spr
    SLICE_X31Y21.X       Tilo                  0.551   DENISE1/hdiwstrt<0>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X30Y20.G4      net (fanout=29)       0.114   AGNUS1/N58
    SLICE_X30Y20.Y       Tilo                  0.608   DENISE1/bplm0/bpl6dat<5>
                                                       AGNUS1/dbr_and000073
    SLICE_X30Y20.F1      net (fanout=8)        0.608   AGNUS1/dbr_and0000
    SLICE_X30Y20.X       Tilo                  0.608   DENISE1/bplm0/bpl6dat<5>
                                                       AGNUS1/dbr
    SLICE_X30Y37.F1      net (fanout=38)       1.174   dbr
    SLICE_X30Y37.X       Tilo                  0.608   turbo
                                                       CPU1/enable114
    SLICE_X30Y36.G1      net (fanout=2)        0.590   CPU1/enable114
    SLICE_X30Y36.Y       Tilo                  0.608   CLOCK1/clocks_ready_pipe<0>
                                                       CPU1/enable
    SLICE_X30Y38.G1      net (fanout=7)        0.552   enable
    SLICE_X30Y38.Y       Tilo                  0.608   DENISE1/col0/clxcon<1>
                                                       CPU1/hwr1
    SLICE_X29Y27.G1      net (fanout=30)       1.247   cpu_hwr
    SLICE_X29Y27.Y       Tilo                  0.551   AGNUS1/N31
                                                       AGNUS1/reg_address<1>1197
    SLICE_X29Y27.F4      net (fanout=1)        0.015   AGNUS1/reg_address<1>1197/O
    SLICE_X29Y27.X       Tilo                  0.551   AGNUS1/N31
                                                       AGNUS1/reg_address<1>11118
    SLICE_X29Y23.G1      net (fanout=9)        0.727   AGNUS1/N31
    SLICE_X29Y23.Y       Tilo                  0.551   DENISE1/sprm0/sps5/datla<13>
                                                       AGNUS1/reg_address<5>109
    SLICE_X41Y17.F2      net (fanout=54)       2.970   reg_address<5>
    SLICE_X41Y17.X       Tilo                  0.551   AGNUS1/bltcon0_11
                                                       AGNUS1/bl1/bltcon0_7_or000021
    SLICE_X47Y13.G4      net (fanout=10)       1.446   AGNUS1/bl1/N27
    SLICE_X47Y13.Y       Tilo                  0.551   DENISE1/sprm0/sps6/datlb<10>
                                                       AGNUS1/bl1/busy_or00001
    SLICE_X32Y25.BY      net (fanout=9)        2.733   AGNUS1/bl1/busy_or0000
    SLICE_X32Y25.CLK     Tsrck                 1.169   busy_0
                                                       AGNUS1/bl1/busy
    -------------------------------------------------  ---------------------------
    Total                                     23.504ns (9.337ns logic, 14.167ns route)
                                                       (39.7% logic, 60.3% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/busy: via_done setup
Slack (setup path):     22.876ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          AGNUS1/bl1/busy (FF)
  Requirement:          35.243ns
  Data Path Delay:      12.010ns (Levels of Logic = 6)
  Clock Path Skew:      -0.003ns (1.839 - 1.842)
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to AGNUS1/bl1/busy
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X30Y17.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.G2      net (fanout=1)        0.841   AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.Y       Tilo                  0.551   _l_data_7
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y19.F3      net (fanout=6)        0.397   AGNUS1/N1_0
    SLICE_X29Y19.X       Tilo                  0.551   _l_data_7
                                                       AGNUS1/dma_spr1
    SLICE_X31Y21.F3      net (fanout=30)       0.753   dma_spr
    SLICE_X31Y21.X       Tilo                  0.551   DENISE1/hdiwstrt<0>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X30Y20.G4      net (fanout=29)       0.114   AGNUS1/N58
    SLICE_X30Y20.Y       Tilo                  0.608   DENISE1/bplm0/bpl6dat<5>
                                                       AGNUS1/dbr_and000073
    SLICE_X19Y10.G3      net (fanout=8)        1.376   AGNUS1/dbr_and0000
    SLICE_X19Y10.Y       Tilo                  0.551   GARY1/ram_address_out<18>42
                                                       AGNUS1/address_out<10>111
    SLICE_X39Y14.G3      net (fanout=24)       2.490   N33_1
    SLICE_X39Y14.Y       Tilo                  0.551   DENISE1/sprm0/sps3/hstart<1>
                                                       AGNUS1/bl1/done
    SLICE_X32Y25.CE      net (fanout=3)        1.354   int3
    SLICE_X32Y25.CLK     Tceck                 0.602   busy_0
                                                       AGNUS1/bl1/busy
    -------------------------------------------------  ---------------------------
    Total                                     12.010ns (4.685ns logic, 7.325ns route)
                                                       (39.0% logic, 61.0% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/busy: all hold
Slack (hold path):      2.234ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/bl1/blt_state_FSM_FFd4 (FF)
  Destination:          AGNUS1/bl1/busy (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.568ns (Levels of Logic = 1)
  Clock Path Skew:      -0.020ns (0.296 - 0.316)
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/bl1/blt_state_FSM_FFd4 to AGNUS1/bl1/busy
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y15.XQ      Tcko                  0.576   AGNUS1/blt_state_FSM_FFd4
                                                       AGNUS1/bl1/blt_state_FSM_FFd4
    SLICE_X39Y14.G2      net (fanout=10)       0.468   AGNUS1/blt_state_FSM_FFd4
    SLICE_X39Y14.Y       Tilo                  0.441   DENISE1/sprm0/sps3/hstart<1>
                                                       AGNUS1/bl1/done
    SLICE_X32Y25.CE      net (fanout=3)        1.083   int3
    SLICE_X32Y25.CLK     Tckce       (-Th)     0.000   busy_0
                                                       AGNUS1/bl1/busy
    -------------------------------------------------  ---------------------------
    Total                                      2.568ns (1.017ns logic, 1.551ns route)
                                                       (39.6% logic, 60.4% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/busy: via_done hold
Slack (hold path):      2.234ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/bl1/blt_state_FSM_FFd4 (FF)
  Destination:          AGNUS1/bl1/busy (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.568ns (Levels of Logic = 1)
  Clock Path Skew:      -0.020ns (0.296 - 0.316)
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/bl1/blt_state_FSM_FFd4 to AGNUS1/bl1/busy
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y15.XQ      Tcko                  0.576   AGNUS1/blt_state_FSM_FFd4
                                                       AGNUS1/bl1/blt_state_FSM_FFd4
    SLICE_X39Y14.G2      net (fanout=10)       0.468   AGNUS1/blt_state_FSM_FFd4
    SLICE_X39Y14.Y       Tilo                  0.441   DENISE1/sprm0/sps3/hstart<1>
                                                       AGNUS1/bl1/done
    SLICE_X32Y25.CE      net (fanout=3)        1.083   int3
    SLICE_X32Y25.CLK     Tckce       (-Th)     0.000   busy_0
                                                       AGNUS1/bl1/busy
    -------------------------------------------------  ---------------------------
    Total                                      2.568ns (1.017ns logic, 1.551ns route)
                                                       (39.6% logic, 60.4% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/start: all setup
Slack (setup path):     21.181ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          AGNUS1/bl1/start (FF)
  Requirement:          35.243ns
  Data Path Delay:      13.706ns (Levels of Logic = 7)
  Clock Path Skew:      -0.002ns (1.840 - 1.842)
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to AGNUS1/bl1/start
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X30Y17.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.G2      net (fanout=1)        0.841   AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.Y       Tilo                  0.551   _l_data_7
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y19.F3      net (fanout=6)        0.397   AGNUS1/N1_0
    SLICE_X29Y19.X       Tilo                  0.551   _l_data_7
                                                       AGNUS1/dma_spr1
    SLICE_X31Y21.F3      net (fanout=30)       0.753   dma_spr
    SLICE_X31Y21.X       Tilo                  0.551   DENISE1/hdiwstrt<0>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X30Y20.G4      net (fanout=29)       0.114   AGNUS1/N58
    SLICE_X30Y20.Y       Tilo                  0.608   DENISE1/bplm0/bpl6dat<5>
                                                       AGNUS1/dbr_and000073
    SLICE_X19Y10.G3      net (fanout=8)        1.376   AGNUS1/dbr_and0000
    SLICE_X19Y10.Y       Tilo                  0.551   GARY1/ram_address_out<18>42
                                                       AGNUS1/address_out<10>111
    SLICE_X39Y14.G3      net (fanout=24)       2.490   N33_1
    SLICE_X39Y14.Y       Tilo                  0.551   DENISE1/sprm0/sps3/hstart<1>
                                                       AGNUS1/bl1/done
    SLICE_X39Y14.F2      net (fanout=3)        0.577   int3
    SLICE_X39Y14.X       Tilo                  0.551   DENISE1/sprm0/sps3/hstart<1>
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X43Y18.SR      net (fanout=2)        1.498   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X43Y18.CLK     Tsrck                 1.026   AGNUS1/bl1/start
                                                       AGNUS1/bl1/start
    -------------------------------------------------  ---------------------------
    Total                                     13.706ns (5.660ns logic, 8.046ns route)
                                                       (41.3% logic, 58.7% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/start: via_done setup
Slack (setup path):     21.181ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          AGNUS1/bl1/start (FF)
  Requirement:          35.243ns
  Data Path Delay:      13.706ns (Levels of Logic = 7)
  Clock Path Skew:      -0.002ns (1.840 - 1.842)
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to AGNUS1/bl1/start
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X30Y17.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.G2      net (fanout=1)        0.841   AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.Y       Tilo                  0.551   _l_data_7
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y19.F3      net (fanout=6)        0.397   AGNUS1/N1_0
    SLICE_X29Y19.X       Tilo                  0.551   _l_data_7
                                                       AGNUS1/dma_spr1
    SLICE_X31Y21.F3      net (fanout=30)       0.753   dma_spr
    SLICE_X31Y21.X       Tilo                  0.551   DENISE1/hdiwstrt<0>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X30Y20.G4      net (fanout=29)       0.114   AGNUS1/N58
    SLICE_X30Y20.Y       Tilo                  0.608   DENISE1/bplm0/bpl6dat<5>
                                                       AGNUS1/dbr_and000073
    SLICE_X19Y10.G3      net (fanout=8)        1.376   AGNUS1/dbr_and0000
    SLICE_X19Y10.Y       Tilo                  0.551   GARY1/ram_address_out<18>42
                                                       AGNUS1/address_out<10>111
    SLICE_X39Y14.G3      net (fanout=24)       2.490   N33_1
    SLICE_X39Y14.Y       Tilo                  0.551   DENISE1/sprm0/sps3/hstart<1>
                                                       AGNUS1/bl1/done
    SLICE_X39Y14.F2      net (fanout=3)        0.577   int3
    SLICE_X39Y14.X       Tilo                  0.551   DENISE1/sprm0/sps3/hstart<1>
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X43Y18.SR      net (fanout=2)        1.498   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X43Y18.CLK     Tsrck                 1.026   AGNUS1/bl1/start
                                                       AGNUS1/bl1/start
    -------------------------------------------------  ---------------------------
    Total                                     13.706ns (5.660ns logic, 8.046ns route)
                                                       (41.3% logic, 58.7% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/start: all hold
Slack (hold path):      3.230ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/bl1/busy (FF)
  Destination:          AGNUS1/bl1/start (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.231ns (Levels of Logic = 1)
  Clock Path Skew:      0.001ns (0.142 - 0.141)
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: AGNUS1/bl1/busy to AGNUS1/bl1/start
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X32Y25.XQ      Tcko                  0.576   busy_0
                                                       AGNUS1/bl1/busy
    SLICE_X38Y19.G4      net (fanout=5)        1.331   busy_0
    SLICE_X38Y19.Y       Tilo                  0.486   DENISE1/sprm0/sps5/hstart<6>
                                                       AGNUS1/bl1/start_and00001
    SLICE_X43Y18.CE      net (fanout=1)        0.838   AGNUS1/bl1/start_and0000
    SLICE_X43Y18.CLK     Tckce       (-Th)     0.000   AGNUS1/bl1/start
                                                       AGNUS1/bl1/start
    -------------------------------------------------  ---------------------------
    Total                                      3.231ns (1.062ns logic, 2.169ns route)
                                                       (32.9% logic, 67.1% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/start: via_done hold
Slack (hold path):      3.279ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/bl1/blt_state_FSM_FFd4 (FF)
  Destination:          AGNUS1/bl1/start (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.614ns (Levels of Logic = 2)
  Clock Path Skew:      -0.019ns (0.297 - 0.316)
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/bl1/blt_state_FSM_FFd4 to AGNUS1/bl1/start
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y15.XQ      Tcko                  0.576   AGNUS1/blt_state_FSM_FFd4
                                                       AGNUS1/bl1/blt_state_FSM_FFd4
    SLICE_X39Y14.G2      net (fanout=10)       0.468   AGNUS1/blt_state_FSM_FFd4
    SLICE_X39Y14.Y       Tilo                  0.441   DENISE1/sprm0/sps3/hstart<1>
                                                       AGNUS1/bl1/done
    SLICE_X39Y14.F2      net (fanout=3)        0.461   int3
    SLICE_X39Y14.X       Tilo                  0.441   DENISE1/sprm0/sps3/hstart<1>
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X43Y18.SR      net (fanout=2)        1.198   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X43Y18.CLK     Tcksr       (-Th)    -0.029   AGNUS1/bl1/start
                                                       AGNUS1/bl1/start
    -------------------------------------------------  ---------------------------
    Total                                      3.614ns (1.487ns logic, 2.127ns route)
                                                       (41.1% logic, 58.9% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/bltbold_init: all setup
Slack (setup path):     14.222ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          AGNUS1/bl1/bltbold_init (FF)
  Requirement:          35.243ns
  Data Path Delay:      20.664ns (Levels of Logic = 14)
  Clock Path Skew:      -0.003ns (1.839 - 1.842)
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to AGNUS1/bl1/bltbold_init
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X30Y17.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.G2      net (fanout=1)        0.841   AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.Y       Tilo                  0.551   _l_data_7
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y19.F3      net (fanout=6)        0.397   AGNUS1/N1_0
    SLICE_X29Y19.X       Tilo                  0.551   _l_data_7
                                                       AGNUS1/dma_spr1
    SLICE_X31Y21.F3      net (fanout=30)       0.753   dma_spr
    SLICE_X31Y21.X       Tilo                  0.551   DENISE1/hdiwstrt<0>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X30Y20.G4      net (fanout=29)       0.114   AGNUS1/N58
    SLICE_X30Y20.Y       Tilo                  0.608   DENISE1/bplm0/bpl6dat<5>
                                                       AGNUS1/dbr_and000073
    SLICE_X30Y20.F1      net (fanout=8)        0.608   AGNUS1/dbr_and0000
    SLICE_X30Y20.X       Tilo                  0.608   DENISE1/bplm0/bpl6dat<5>
                                                       AGNUS1/dbr
    SLICE_X30Y37.F1      net (fanout=38)       1.174   dbr
    SLICE_X30Y37.X       Tilo                  0.608   turbo
                                                       CPU1/enable114
    SLICE_X30Y36.G1      net (fanout=2)        0.590   CPU1/enable114
    SLICE_X30Y36.Y       Tilo                  0.608   CLOCK1/clocks_ready_pipe<0>
                                                       CPU1/enable
    SLICE_X30Y38.G1      net (fanout=7)        0.552   enable
    SLICE_X30Y38.Y       Tilo                  0.608   DENISE1/col0/clxcon<1>
                                                       CPU1/hwr1
    SLICE_X29Y27.G1      net (fanout=30)       1.247   cpu_hwr
    SLICE_X29Y27.Y       Tilo                  0.551   AGNUS1/N31
                                                       AGNUS1/reg_address<1>1197
    SLICE_X29Y27.F4      net (fanout=1)        0.015   AGNUS1/reg_address<1>1197/O
    SLICE_X29Y27.X       Tilo                  0.551   AGNUS1/N31
                                                       AGNUS1/reg_address<1>11118
    SLICE_X26Y20.G1      net (fanout=9)        0.983   AGNUS1/N31
    SLICE_X26Y20.Y       Tilo                  0.608   AGNUS1/bc1/N1042
                                                       AGNUS1/reg_address<8>61
    SLICE_X41Y17.G1      net (fanout=37)       1.586   reg_address<8>
    SLICE_X41Y17.Y       Tilo                  0.551   AGNUS1/bltcon0_11
                                                       AGNUS1/bl1/address_generator_1/bltpth_3_or000021
    SLICE_X49Y18.G2      net (fanout=5)        1.297   AGNUS1/bl1/N5_0
    SLICE_X49Y18.Y       Tilo                  0.551   CPU1/invalidate_sync<1>
                                                       AGNUS1/bl1/bltadat_cmp_eq000012
    SLICE_X49Y18.F3      net (fanout=4)        0.043   AGNUS1/bl1/N24
    SLICE_X49Y18.X       Tilo                  0.551   CPU1/invalidate_sync<1>
                                                       AGNUS1/bl1/bltbdat_cmp_eq00001
    SLICE_X47Y21.CE      net (fanout=21)       1.086   AGNUS1/bl1/bltbdat_cmp_eq0000
    SLICE_X47Y21.CLK     Tceck                 0.602   AGNUS1/bl1/bltbold_init
                                                       AGNUS1/bl1/bltbold_init
    -------------------------------------------------  ---------------------------
    Total                                     20.664ns (9.378ns logic, 11.286ns route)
                                                       (45.4% logic, 54.6% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/bltbold_init: via_done setup
Slack (setup path):     20.755ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          AGNUS1/bl1/bltbold_init (FF)
  Requirement:          35.243ns
  Data Path Delay:      14.131ns (Levels of Logic = 7)
  Clock Path Skew:      -0.003ns (1.839 - 1.842)
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to AGNUS1/bl1/bltbold_init
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X30Y17.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.G2      net (fanout=1)        0.841   AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.Y       Tilo                  0.551   _l_data_7
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y19.F3      net (fanout=6)        0.397   AGNUS1/N1_0
    SLICE_X29Y19.X       Tilo                  0.551   _l_data_7
                                                       AGNUS1/dma_spr1
    SLICE_X31Y21.F3      net (fanout=30)       0.753   dma_spr
    SLICE_X31Y21.X       Tilo                  0.551   DENISE1/hdiwstrt<0>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X30Y20.G4      net (fanout=29)       0.114   AGNUS1/N58
    SLICE_X30Y20.Y       Tilo                  0.608   DENISE1/bplm0/bpl6dat<5>
                                                       AGNUS1/dbr_and000073
    SLICE_X19Y10.G3      net (fanout=8)        1.376   AGNUS1/dbr_and0000
    SLICE_X19Y10.Y       Tilo                  0.551   GARY1/ram_address_out<18>42
                                                       AGNUS1/address_out<10>111
    SLICE_X39Y14.G3      net (fanout=24)       2.490   N33_1
    SLICE_X39Y14.Y       Tilo                  0.551   DENISE1/sprm0/sps3/hstart<1>
                                                       AGNUS1/bl1/done
    SLICE_X39Y14.F2      net (fanout=3)        0.577   int3
    SLICE_X39Y14.X       Tilo                  0.551   DENISE1/sprm0/sps3/hstart<1>
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X47Y21.SR      net (fanout=2)        1.923   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X47Y21.CLK     Tsrck                 1.026   AGNUS1/bl1/bltbold_init
                                                       AGNUS1/bl1/bltbold_init
    -------------------------------------------------  ---------------------------
    Total                                     14.131ns (5.660ns logic, 8.471ns route)
                                                       (40.1% logic, 59.9% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/bltbold_init: all hold
Slack (hold path):      3.620ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/bl1/blt_state_FSM_FFd4 (FF)
  Destination:          AGNUS1/bl1/bltbold_init (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.954ns (Levels of Logic = 2)
  Clock Path Skew:      -0.020ns (0.296 - 0.316)
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/bl1/blt_state_FSM_FFd4 to AGNUS1/bl1/bltbold_init
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y15.XQ      Tcko                  0.576   AGNUS1/blt_state_FSM_FFd4
                                                       AGNUS1/bl1/blt_state_FSM_FFd4
    SLICE_X39Y14.G2      net (fanout=10)       0.468   AGNUS1/blt_state_FSM_FFd4
    SLICE_X39Y14.Y       Tilo                  0.441   DENISE1/sprm0/sps3/hstart<1>
                                                       AGNUS1/bl1/done
    SLICE_X39Y14.F2      net (fanout=3)        0.461   int3
    SLICE_X39Y14.X       Tilo                  0.441   DENISE1/sprm0/sps3/hstart<1>
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X47Y21.SR      net (fanout=2)        1.538   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X47Y21.CLK     Tcksr       (-Th)    -0.029   AGNUS1/bl1/bltbold_init
                                                       AGNUS1/bl1/bltbold_init
    -------------------------------------------------  ---------------------------
    Total                                      3.954ns (1.487ns logic, 2.467ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/bltbold_init: via_done hold
Slack (hold path):      3.620ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/bl1/blt_state_FSM_FFd4 (FF)
  Destination:          AGNUS1/bl1/bltbold_init (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.954ns (Levels of Logic = 2)
  Clock Path Skew:      -0.020ns (0.296 - 0.316)
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/bl1/blt_state_FSM_FFd4 to AGNUS1/bl1/bltbold_init
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y15.XQ      Tcko                  0.576   AGNUS1/blt_state_FSM_FFd4
                                                       AGNUS1/bl1/blt_state_FSM_FFd4
    SLICE_X39Y14.G2      net (fanout=10)       0.468   AGNUS1/blt_state_FSM_FFd4
    SLICE_X39Y14.Y       Tilo                  0.441   DENISE1/sprm0/sps3/hstart<1>
                                                       AGNUS1/bl1/done
    SLICE_X39Y14.F2      net (fanout=3)        0.461   int3
    SLICE_X39Y14.X       Tilo                  0.441   DENISE1/sprm0/sps3/hstart<1>
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X47Y21.SR      net (fanout=2)        1.538   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X47Y21.CLK     Tcksr       (-Th)    -0.029   AGNUS1/bl1/bltbold_init
                                                       AGNUS1/bl1/bltbold_init
    -------------------------------------------------  ---------------------------
    Total                                      3.954ns (1.487ns logic, 2.467ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------


PAULA1/pi1/intreq_6: all setup
Slack (setup path):     12.617ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          PAULA1/pi1/intreq_6 (FF)
  Requirement:          35.243ns
  Data Path Delay:      22.269ns (Levels of Logic = 13)
  Clock Path Skew:      -0.003ns (1.839 - 1.842)
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to PAULA1/pi1/intreq_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X30Y17.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.G2      net (fanout=1)        0.841   AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.Y       Tilo                  0.551   _l_data_7
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y19.F3      net (fanout=6)        0.397   AGNUS1/N1_0
    SLICE_X29Y19.X       Tilo                  0.551   _l_data_7
                                                       AGNUS1/dma_spr1
    SLICE_X12Y13.G3      net (fanout=30)       2.644   dma_spr
    SLICE_X12Y13.Y       Tilo                  0.608   AGNUS1/sprite_1
                                                       AGNUS1/address_out<10>131
    SLICE_X13Y11.G4      net (fanout=7)        0.434   AGNUS1/N41
    SLICE_X13Y11.X       Tif5x                 0.911   MIA1/profile_sample<0>
                                                       AGNUS1/address_out<20>11_F
                                                       AGNUS1/address_out<20>11
    SLICE_X18Y12.F2      net (fanout=1)        1.524   AGNUS1/address_out<20>11
    SLICE_X18Y12.X       Tilo                  0.608   dma_address_out<20>
                                                       AGNUS1/address_out<20>54
    SLICE_X16Y24.G4      net (fanout=5)        2.522   dma_address_out<20>
    SLICE_X16Y24.Y       Tilo                  0.608   USERIO1/osd1/spi0/first_byte
                                                       GARY1/sel_slow_0_mux000016
    SLICE_X16Y24.F4      net (fanout=1)        0.015   GARY1/sel_slow_0_mux000016/O
    SLICE_X16Y24.X       Tilo                  0.608   USERIO1/osd1/spi0/first_byte
                                                       GARY1/sel_chip_1_mux00001
    SLICE_X17Y24.F4      net (fanout=4)        0.041   sel_chip<1>
    SLICE_X17Y24.X       Tilo                  0.551   USERIO1/osd1/wrdat<3>
                                                       memory_config<0>1
    SLICE_X17Y25.F2      net (fanout=1)        0.209   memory_config<0>1
    SLICE_X17Y25.X       Tif5x                 0.911   USERIO1/osd1/t_memory_config<2>
                                                       BMAP1/Mmux_bank_3
                                                       BMAP1/Mmux_bank_2_f5
    SLICE_X12Y24.G2      net (fanout=3)        0.999   bank<1>
    SLICE_X12Y24.Y       Tilo                  0.608   AGNUS1/bpd1/vdiwstrt<8>
                                                       RAM1/enable81
    SLICE_X24Y21.G2      net (fanout=25)       2.560   enable_0
    SLICE_X24Y21.Y       Tilo                  0.608   AGNUS1/bpd1/vdiwstop<7>
                                                       RAM1/data_out<15>1
    SLICE_X24Y21.F3      net (fanout=5)        0.031   ram_data_out<15>
    SLICE_X24Y21.X       Tilo                  0.608   AGNUS1/bpd1/vdiwstop<7>
                                                       GARY1/custom_data_in<15>1
    SLICE_X39Y21.G3      net (fanout=131)      0.968   custom_data_in<15>
    SLICE_X39Y21.CLK     Tgck                  0.633   intreq_6
                                                       PAULA1/pi1/intreq_6_or00001
                                                       PAULA1/pi1/intreq_6
    -------------------------------------------------  ---------------------------
    Total                                     22.269ns (9.084ns logic, 13.185ns route)
                                                       (40.8% logic, 59.2% route)

--------------------------------------------------------------------------------


PAULA1/pi1/intreq_6: via_done setup
Slack (setup path):     22.490ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          PAULA1/pi1/intreq_6 (FF)
  Requirement:          35.243ns
  Data Path Delay:      12.396ns (Levels of Logic = 6)
  Clock Path Skew:      -0.003ns (1.839 - 1.842)
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to PAULA1/pi1/intreq_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X30Y17.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.G2      net (fanout=1)        0.841   AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.Y       Tilo                  0.551   _l_data_7
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y19.F3      net (fanout=6)        0.397   AGNUS1/N1_0
    SLICE_X29Y19.X       Tilo                  0.551   _l_data_7
                                                       AGNUS1/dma_spr1
    SLICE_X31Y21.F3      net (fanout=30)       0.753   dma_spr
    SLICE_X31Y21.X       Tilo                  0.551   DENISE1/hdiwstrt<0>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X30Y20.G4      net (fanout=29)       0.114   AGNUS1/N58
    SLICE_X30Y20.Y       Tilo                  0.608   DENISE1/bplm0/bpl6dat<5>
                                                       AGNUS1/dbr_and000073
    SLICE_X19Y10.G3      net (fanout=8)        1.376   AGNUS1/dbr_and0000
    SLICE_X19Y10.Y       Tilo                  0.551   GARY1/ram_address_out<18>42
                                                       AGNUS1/address_out<10>111
    SLICE_X39Y14.G3      net (fanout=24)       2.490   N33_1
    SLICE_X39Y14.Y       Tilo                  0.551   DENISE1/sprm0/sps3/hstart<1>
                                                       AGNUS1/bl1/done
    SLICE_X39Y21.BY      net (fanout=3)        1.173   int3
    SLICE_X39Y21.CLK     Tsrck                 1.169   intreq_6
                                                       PAULA1/pi1/intreq_6
    -------------------------------------------------  ---------------------------
    Total                                     12.396ns (5.252ns logic, 7.144ns route)
                                                       (42.4% logic, 57.6% route)

--------------------------------------------------------------------------------


PAULA1/pi1/intreq_6: all hold
Slack (hold path):      0.953ns (requirement - (clock path skew + uncertainty - data path))
  Source:               PAULA1/pi1/intreq_6 (FF)
  Destination:          PAULA1/pi1/intreq_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.953ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: PAULA1/pi1/intreq_6 to PAULA1/pi1/intreq_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X39Y21.YQ      Tcko                  0.576   intreq_6
                                                       PAULA1/pi1/intreq_6
    SLICE_X39Y21.G4      net (fanout=3)        0.316   intreq_6
    SLICE_X39Y21.CLK     Tckg        (-Th)    -0.061   intreq_6
                                                       PAULA1/pi1/intreq_6_or00001
                                                       PAULA1/pi1/intreq_6
    -------------------------------------------------  ---------------------------
    Total                                      0.953ns (0.637ns logic, 0.316ns route)
                                                       (66.8% logic, 33.2% route)

--------------------------------------------------------------------------------



PAULA1/pi1/intreq_6: via_done hold
Slack (hold path):      2.233ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/bl1/blt_state_FSM_FFd4 (FF)
  Destination:          PAULA1/pi1/intreq_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.567ns (Levels of Logic = 1)
  Clock Path Skew:      -0.020ns (0.296 - 0.316)
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/bl1/blt_state_FSM_FFd4 to PAULA1/pi1/intreq_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y15.XQ      Tcko                  0.576   AGNUS1/blt_state_FSM_FFd4
                                                       AGNUS1/bl1/blt_state_FSM_FFd4
    SLICE_X39Y14.G2      net (fanout=10)       0.468   AGNUS1/blt_state_FSM_FFd4
    SLICE_X39Y14.Y       Tilo                  0.441   DENISE1/sprm0/sps3/hstart<1>
                                                       AGNUS1/bl1/done
    SLICE_X39Y21.BY      net (fanout=3)        0.939   int3
    SLICE_X39Y21.CLK     Tcksr       (-Th)    -0.143   intreq_6
                                                       PAULA1/pi1/intreq_6
    -------------------------------------------------  ---------------------------
    Total                                      2.567ns (1.160ns logic, 1.407ns route)
                                                       (45.2% logic, 54.8% route)

--------------------------------------------------------------------------------


Related clk28 via_done: reported setup
Slack (setup path):     20.755ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          AGNUS1/bl1/bltbold_init (FF)
  Requirement:          35.243ns
  Data Path Delay:      14.131ns (Levels of Logic = 7)
  Clock Path Skew:      -0.003ns (1.839 - 1.842)
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to AGNUS1/bl1/bltbold_init
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X30Y17.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.G2      net (fanout=1)        0.841   AGNUS1/spr1/sprdmastate
    SLICE_X29Y19.Y       Tilo                  0.551   _l_data_7
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y19.F3      net (fanout=6)        0.397   AGNUS1/N1_0
    SLICE_X29Y19.X       Tilo                  0.551   _l_data_7
                                                       AGNUS1/dma_spr1
    SLICE_X31Y21.F3      net (fanout=30)       0.753   dma_spr
    SLICE_X31Y21.X       Tilo                  0.551   DENISE1/hdiwstrt<0>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X30Y20.G4      net (fanout=29)       0.114   AGNUS1/N58
    SLICE_X30Y20.Y       Tilo                  0.608   DENISE1/bplm0/bpl6dat<5>
                                                       AGNUS1/dbr_and000073
    SLICE_X19Y10.G3      net (fanout=8)        1.376   AGNUS1/dbr_and0000
    SLICE_X19Y10.Y       Tilo                  0.551   GARY1/ram_address_out<18>42
                                                       AGNUS1/address_out<10>111
    SLICE_X39Y14.G3      net (fanout=24)       2.490   N33_1
    SLICE_X39Y14.Y       Tilo                  0.551   DENISE1/sprm0/sps3/hstart<1>
                                                       AGNUS1/bl1/done
    SLICE_X39Y14.F2      net (fanout=3)        0.577   int3
    SLICE_X39Y14.X       Tilo                  0.551   DENISE1/sprm0/sps3/hstart<1>
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X47Y21.SR      net (fanout=2)        1.923   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X47Y21.CLK     Tsrck                 1.026   AGNUS1/bl1/bltbold_init
                                                       AGNUS1/bl1/bltbold_init
    -------------------------------------------------  ---------------------------
    Total                                     14.131ns (5.660ns logic, 8.471ns route)
                                                       (40.1% logic, 59.9% route)

--------------------------------------------------------------------------------


Related clk28 via_done: reported hold
Slack (hold path):      7.221ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/spr1/sprvstop (FF)
  Destination:          PAULA1/pi1/intreq_6 (FF)
  Requirement:          -0.001ns
  Data Path Delay:      7.573ns (Levels of Logic = 5)
  Clock Path Skew:      -0.003ns (1.839 - 1.842)
  Source Clock:         clk28m rising at 422.904ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/spr1/sprvstop to PAULA1/pi1/intreq_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X31Y18.YQ      Tcko                  0.576   AGNUS1/sprvstop
                                                       AGNUS1/spr1/sprvstop
    SLICE_X29Y19.G3      net (fanout=2)        0.626   AGNUS1/sprvstop
    SLICE_X29Y19.Y       Tilo                  0.441   _l_data_7
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y19.F3      net (fanout=6)        0.318   AGNUS1/N1_0
    SLICE_X29Y19.X       Tilo                  0.441   _l_data_7
                                                       AGNUS1/dma_spr1
    SLICE_X31Y21.F3      net (fanout=30)       0.602   dma_spr
    SLICE_X31Y21.X       Tilo                  0.441   DENISE1/hdiwstrt<0>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X38Y11.F4      net (fanout=29)       1.578   AGNUS1/N58
    SLICE_X38Y11.X       Tilo                  0.486   DENISE1/sprm0/sps2/hstart<5>
                                                       AGNUS1/bl1/done_SW1
    SLICE_X39Y14.G1      net (fanout=1)        0.541   AGNUS1/bl1/N1174
    SLICE_X39Y14.Y       Tilo                  0.441   DENISE1/sprm0/sps3/hstart<1>
                                                       AGNUS1/bl1/done
    SLICE_X39Y21.BY      net (fanout=3)        0.939   int3
    SLICE_X39Y21.CLK     Tcksr       (-Th)    -0.143   intreq_6
                                                       PAULA1/pi1/intreq_6
    -------------------------------------------------  ---------------------------
    Total                                      7.573ns (2.969ns logic, 4.604ns route)
                                                       (39.2% logic, 60.8% route)

--------------------------------------------------------------------------------
