Timing constraint: TS_R3_LOCAL_COMPLETION = MAXDELAY FROM TIMEGRP 
"R3_LOCAL_ACK" TO TIMEGRP "R3_LOCAL_REQUEST" 1000 ns DATAPATHONLY;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   5.371ns.
--------------------------------------------------------------------------------

Paths for end point CPU1/l_as28m (SLICE_X36Y44.SR), 1 path
--------------------------------------------------------------------------------
Slack (setup paths):    994.629ns (requirement - (data path - clock path skew + uncertainty))
  Source:               CPU1/_ta_t1 (FF)
  Destination:          CPU1/l_as28m (FF)
  Requirement:          1000.000ns
  Data Path Delay:      5.371ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: CPU1/_ta_t1 to CPU1/l_as28m
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X35Y43.YQ      Tcko                  0.720   CPU1/_ta_t1
                                                       CPU1/_ta_t1
    SLICE_X45Y43.G4      net (fanout=2)        1.574   CPU1/_ta_t1
    SLICE_X45Y43.X       Tif5x                 0.911   CPU1/_ta_t2
                                                       CPU1/l_as28m_or0000121
                                                       CPU1/l_as28m_or000012_f5
    SLICE_X36Y44.SR      net (fanout=1)        1.140   CPU1/l_as28m_or000012
    SLICE_X36Y44.CLK     Tsrck                 1.026   CPU1/l_as28m
                                                       CPU1/l_as28m
    -------------------------------------------------  ---------------------------
    Total                                      5.371ns (2.657ns logic, 2.714ns route)
                                                       (49.5% logic, 50.5% route)

--------------------------------------------------------------------------------

Fastest Paths: TS_R3_LOCAL_COMPLETION = MAXDELAY FROM TIMEGRP "R3_LOCAL_ACK" TO TIMEGRP "R3_LOCAL_REQUEST" 1000 ns DATAPATHONLY;
--------------------------------------------------------------------------------

Paths for end point CPU1/l_as28m (SLICE_X36Y44.SR), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      3.506ns (requirement - (clock path skew + uncertainty - data path))
  Source:               CPU1/_ta_t1 (FF)
  Destination:          CPU1/l_as28m (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.506ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 422.904ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: CPU1/_ta_t1 to CPU1/l_as28m
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X35Y43.YQ      Tcko                  0.576   CPU1/_ta_t1
                                                       CPU1/_ta_t1
    SLICE_X45Y43.G4      net (fanout=2)        1.260   CPU1/_ta_t1
    SLICE_X45Y43.X       Tif5x                 0.729   CPU1/_ta_t2
                                                       CPU1/l_as28m_or0000121
                                                       CPU1/l_as28m_or000012_f5
    SLICE_X36Y44.SR      net (fanout=1)        0.912   CPU1/l_as28m_or000012
    SLICE_X36Y44.CLK     Tcksr       (-Th)    -0.029   CPU1/l_as28m
                                                       CPU1/l_as28m
    -------------------------------------------------  ---------------------------
    Total                                      3.506ns (1.334ns logic, 2.172ns route)
                                                       (38.0% logic, 62.0% route)

--------------------------------------------------------------------------------

================================================================================

Timing constraint: TS_R3_FIRST_SYNC = MAXDELAY FROM TIMEGRP "R3_LOCAL_ACK" TO 
TIMEGRP "R3_CPU_SYNC1" 1000 ns DATAPATHONLY;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   3.210ns.
--------------------------------------------------------------------------------

Paths for end point CPU1/_ta_t2 (SLICE_X45Y43.CE), 1 path
--------------------------------------------------------------------------------
Slack (setup paths):    996.790ns (requirement - (data path - clock path skew + uncertainty))
  Source:               CPU1/_ta_t1 (FF)
  Destination:          CPU1/_ta_t2 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      3.210ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising
  Destination Clock:    cpu_clk_OBUF rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: CPU1/_ta_t1 to CPU1/_ta_t2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X35Y43.YQ      Tcko                  0.720   CPU1/_ta_t1
                                                       CPU1/_ta_t1
    SLICE_X45Y43.CE      net (fanout=2)        1.888   CPU1/_ta_t1
    SLICE_X45Y43.CLK     Tceck                 0.602   CPU1/_ta_t2
                                                       CPU1/_ta_t2
    -------------------------------------------------  ---------------------------
    Total                                      3.210ns (1.322ns logic, 1.888ns route)
                                                       (41.2% logic, 58.8% route)

--------------------------------------------------------------------------------

Fastest Paths: TS_R3_FIRST_SYNC = MAXDELAY FROM TIMEGRP "R3_LOCAL_ACK" TO TIMEGRP "R3_CPU_SYNC1" 1000 ns DATAPATHONLY;
--------------------------------------------------------------------------------

Paths for end point CPU1/_ta_t2 (SLICE_X45Y43.CE), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      2.087ns (requirement - (clock path skew + uncertainty - data path))
  Source:               CPU1/_ta_t1 (FF)
  Destination:          CPU1/_ta_t2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.087ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising
  Destination Clock:    cpu_clk_OBUF rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: CPU1/_ta_t1 to CPU1/_ta_t2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X35Y43.YQ      Tcko                  0.576   CPU1/_ta_t1
                                                       CPU1/_ta_t1
    SLICE_X45Y43.CE      net (fanout=2)        1.511   CPU1/_ta_t1
    SLICE_X45Y43.CLK     Tckce       (-Th)     0.000   CPU1/_ta_t2
                                                       CPU1/_ta_t2
    -------------------------------------------------  ---------------------------
    Total                                      2.087ns (0.576ns logic, 1.511ns route)
                                                       (27.6% logic, 72.4% route)

--------------------------------------------------------------------------------

================================================================================

Timing constraint: TS_R3_SECOND_SYNC = MAXDELAY FROM TIMEGRP "R3_CPU_SYNC1" TO 
TIMEGRP "R3_CPU_SYNC2" 1000 ns DATAPATHONLY;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   2.150ns.
--------------------------------------------------------------------------------

Paths for end point CPU1/_ta_t (SLICE_X45Y40.CE), 1 path
--------------------------------------------------------------------------------
Slack (setup paths):    997.850ns (requirement - (data path - clock path skew + uncertainty))
  Source:               CPU1/_ta_t2 (FF)
  Destination:          CPU1/_ta_t (FF)
  Requirement:          1000.000ns
  Data Path Delay:      2.150ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         cpu_clk_OBUF rising at 0.000ns
  Destination Clock:    cpu_clk_OBUF rising at 16.584ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: CPU1/_ta_t2 to CPU1/_ta_t
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X45Y43.YQ      Tcko                  0.720   CPU1/_ta_t2
                                                       CPU1/_ta_t2
    SLICE_X45Y40.CE      net (fanout=1)        0.828   CPU1/_ta_t2
    SLICE_X45Y40.CLK     Tceck                 0.602   CPU1/_ta_t
                                                       CPU1/_ta_t
    -------------------------------------------------  ---------------------------
    Total                                      2.150ns (1.322ns logic, 0.828ns route)
                                                       (61.5% logic, 38.5% route)

--------------------------------------------------------------------------------

Fastest Paths: TS_R3_SECOND_SYNC = MAXDELAY FROM TIMEGRP "R3_CPU_SYNC1" TO TIMEGRP "R3_CPU_SYNC2" 1000 ns DATAPATHONLY;
--------------------------------------------------------------------------------

Paths for end point CPU1/_ta_t (SLICE_X45Y40.CE), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      1.238ns (requirement - (clock path skew + uncertainty - data path))
  Source:               CPU1/_ta_t2 (FF)
  Destination:          CPU1/_ta_t (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.238ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         cpu_clk_OBUF rising at 0.000ns
  Destination Clock:    cpu_clk_OBUF rising at 0.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: CPU1/_ta_t2 to CPU1/_ta_t
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X45Y43.YQ      Tcko                  0.576   CPU1/_ta_t2
                                                       CPU1/_ta_t2
    SLICE_X45Y40.CE      net (fanout=1)        0.662   CPU1/_ta_t2
    SLICE_X45Y40.CLK     Tckce       (-Th)     0.000   CPU1/_ta_t
                                                       CPU1/_ta_t
    -------------------------------------------------  ---------------------------
    Total                                      1.238ns (0.576ns logic, 0.662ns route)
                                                       (46.5% logic, 53.5% route)

--------------------------------------------------------------------------------

================================================================================

Timing constraint: TS_R3_RETURN_ACK = MAXDELAY FROM TIMEGRP "R3_CPU_SYNC2" TO 
TIMEGRP "R3_CPU_FEEDBACK" 1000 ns DATAPATHONLY;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   2.081ns.
--------------------------------------------------------------------------------

Paths for end point CPU1/l_dtack (SLICE_X44Y42.F1), 1 path
--------------------------------------------------------------------------------
Slack (setup paths):    997.919ns (requirement - (data path - clock path skew + uncertainty))
  Source:               CPU1/_ta_t (FF)
  Destination:          CPU1/l_dtack (FF)
  Requirement:          1000.000ns
  Data Path Delay:      2.081ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         cpu_clk_OBUF rising
  Destination Clock:    clk rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: CPU1/_ta_t to CPU1/l_dtack
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X45Y40.YQ      Tcko                  0.720   CPU1/_ta_t
                                                       CPU1/_ta_t
    SLICE_X44Y42.F1      net (fanout=3)        0.671   CPU1/_ta_t
    SLICE_X44Y42.CLK     Tfck                  0.690   l_dtack
                                                       CPU1/private_internal_dtack
                                                       CPU1/l_dtack
    -------------------------------------------------  ---------------------------
    Total                                      2.081ns (1.410ns logic, 0.671ns route)
                                                       (67.8% logic, 32.2% route)

--------------------------------------------------------------------------------

Fastest Paths: TS_R3_RETURN_ACK = MAXDELAY FROM TIMEGRP "R3_CPU_SYNC2" TO TIMEGRP "R3_CPU_FEEDBACK" 1000 ns DATAPATHONLY;
--------------------------------------------------------------------------------

Paths for end point CPU1/l_dtack (SLICE_X44Y42.F1), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      1.219ns (requirement - (clock path skew + uncertainty - data path))
  Source:               CPU1/_ta_t (FF)
  Destination:          CPU1/l_dtack (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.219ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         cpu_clk_OBUF rising
  Destination Clock:    clk rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: CPU1/_ta_t to CPU1/l_dtack
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X45Y40.YQ      Tcko                  0.576   CPU1/_ta_t
                                                       CPU1/_ta_t
    SLICE_X44Y42.F1      net (fanout=3)        0.537   CPU1/_ta_t
    SLICE_X44Y42.CLK     Tckf        (-Th)    -0.106   l_dtack
                                                       CPU1/private_internal_dtack
                                                       CPU1/l_dtack
    -------------------------------------------------  ---------------------------
    Total                                      1.219ns (0.682ns logic, 0.537ns route)
                                                       (55.9% logic, 44.1% route)

--------------------------------------------------------------------------------

================================================================================

Timing constraint: TS_R3_CUSTOM_DATA = MAXDELAY FROM TIMEGRP "CPU_DATA" TO 
TIMEGRP "R3_CUSTOM_MASKS" 1000 ns DATAPATHONLY;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 32 paths analyzed, 32 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is  16.458ns.
--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_15 (SLICE_X1Y20.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  983.542ns (requirement - data path)
  Source:               cpu_data<15> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_15 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      16.458ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<15> to AGNUS1/bl1/bltafwm_15
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P135.I               Tiopi                 1.918   cpu_data<15>
                                                       cpu_data<15>
                                                       cpu_data_15_IOBUF/IBUF
    SLICE_X23Y31.F1      net (fanout=27)       4.995   N946
    SLICE_X23Y31.X       Tilo                  0.551   GAYLE1/empty_wr
                                                       gary_cpu_data_in<15>1
    SLICE_X22Y33.F1      net (fanout=5)        3.419   gary_cpu_data_in<15>
    SLICE_X22Y33.X       Tilo                  0.608   AGNUS1/bpd1/vdiwstop<7>
                                                       GARY1/custom_data_in<15>1
    SLICE_X1Y20.BY       net (fanout=131)      4.706   custom_data_in<15>
    SLICE_X1Y20.CLK      Tdick                 0.261   AGNUS1/bl1/bltafwm<12>
                                                       AGNUS1/bl1/bltafwm_15
    -------------------------------------------------  ---------------------------
    Total                                     16.458ns (3.338ns logic, 13.120ns route)
                                                       (20.3% logic, 79.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_15 (SLICE_X1Y17.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  983.881ns (requirement - data path)
  Source:               cpu_data<15> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_15 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      16.119ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<15> to AGNUS1/bl1/bltalwm_15
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P135.I               Tiopi                 1.918   cpu_data<15>
                                                       cpu_data<15>
                                                       cpu_data_15_IOBUF/IBUF
    SLICE_X23Y31.F1      net (fanout=27)       4.995   N946
    SLICE_X23Y31.X       Tilo                  0.551   GAYLE1/empty_wr
                                                       gary_cpu_data_in<15>1
    SLICE_X22Y33.F1      net (fanout=5)        3.419   gary_cpu_data_in<15>
    SLICE_X22Y33.X       Tilo                  0.608   AGNUS1/bpd1/vdiwstop<7>
                                                       GARY1/custom_data_in<15>1
    SLICE_X1Y17.BY       net (fanout=131)      4.367   custom_data_in<15>
    SLICE_X1Y17.CLK      Tdick                 0.261   AGNUS1/bl1/bltalwm<14>
                                                       AGNUS1/bl1/bltalwm_15
    -------------------------------------------------  ---------------------------
    Total                                     16.119ns (3.338ns logic, 12.781ns route)
                                                       (20.7% logic, 79.3% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_6 (SLICE_X13Y17.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  985.874ns (requirement - data path)
  Source:               cpu_data<6> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_6 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      14.126ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<6> to AGNUS1/bl1/bltafwm_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P161.I               Tiopi                 1.918   cpu_data<6>
                                                       cpu_data<6>
                                                       cpu_data_6_IOBUF/IBUF
    SLICE_X27Y24.G4      net (fanout=19)       6.451   N955
    SLICE_X27Y24.Y       Tilo                  0.551   DENISE1/sprm0/sps5/armed
                                                       gary_cpu_data_in<6>1
    SLICE_X19Y15.F1      net (fanout=4)        2.147   gary_cpu_data_in<6>
    SLICE_X19Y15.X       Tilo                  0.551   AGNUS1/bl1/bltadat<6>
                                                       GARY1/custom_data_in<6>1
    SLICE_X13Y17.BY      net (fanout=91)       2.247   custom_data_in<6>
    SLICE_X13Y17.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<5>
                                                       AGNUS1/bl1/bltafwm_6
    -------------------------------------------------  ---------------------------
    Total                                     14.126ns (3.281ns logic, 10.845ns route)
                                                       (23.2% logic, 76.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_12 (SLICE_X1Y20.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  985.979ns (requirement - data path)
  Source:               cpu_data<12> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_12 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      14.021ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<12> to AGNUS1/bl1/bltafwm_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P141.I               Tiopi                 1.918   cpu_data<12>
                                                       cpu_data<12>
                                                       cpu_data_12_IOBUF/IBUF
    SLICE_X22Y25.F1      net (fanout=23)       4.790   N949
    SLICE_X22Y25.X       Tilo                  0.608   cpu_address_out<6>
                                                       gary_cpu_data_in<12>1
    SLICE_X23Y24.F4      net (fanout=4)        0.374   gary_cpu_data_in<12>
    SLICE_X23Y24.X       Tilo                  0.551   AGNUS1/bl1/height<12>
                                                       GARY1/custom_data_in<12>1
    SLICE_X1Y20.BX       net (fanout=70)       5.577   custom_data_in<12>
    SLICE_X1Y20.CLK      Tdick                 0.203   AGNUS1/bl1/bltafwm<12>
                                                       AGNUS1/bl1/bltafwm_12
    -------------------------------------------------  ---------------------------
    Total                                     14.021ns (3.280ns logic, 10.741ns route)
                                                       (23.4% logic, 76.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_12 (SLICE_X1Y21.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  985.979ns (requirement - data path)
  Source:               cpu_data<12> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_12 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      14.021ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<12> to AGNUS1/bl1/bltalwm_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P141.I               Tiopi                 1.918   cpu_data<12>
                                                       cpu_data<12>
                                                       cpu_data_12_IOBUF/IBUF
    SLICE_X22Y25.F1      net (fanout=23)       4.790   N949
    SLICE_X22Y25.X       Tilo                  0.608   cpu_address_out<6>
                                                       gary_cpu_data_in<12>1
    SLICE_X23Y24.F4      net (fanout=4)        0.374   gary_cpu_data_in<12>
    SLICE_X23Y24.X       Tilo                  0.551   AGNUS1/bl1/height<12>
                                                       GARY1/custom_data_in<12>1
    SLICE_X1Y21.BX       net (fanout=70)       5.577   custom_data_in<12>
    SLICE_X1Y21.CLK      Tdick                 0.203   AGNUS1/bl1/bltalwm<12>
                                                       AGNUS1/bl1/bltalwm_12
    -------------------------------------------------  ---------------------------
    Total                                     14.021ns (3.280ns logic, 10.741ns route)
                                                       (23.4% logic, 76.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_7 (SLICE_X12Y18.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  986.033ns (requirement - data path)
  Source:               cpu_data<7> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_7 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      13.967ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<7> to AGNUS1/bl1/bltafwm_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P155.I               Tiopi                 1.918   cpu_data<7>
                                                       cpu_data<7>
                                                       cpu_data_7_IOBUF/IBUF
    SLICE_X27Y21.G2      net (fanout=22)       5.626   N954
    SLICE_X27Y21.Y       Tilo                  0.551   MIA1/magic_r_w<12>
                                                       gary_cpu_data_in<7>1
    SLICE_X22Y17.F2      net (fanout=5)        2.130   gary_cpu_data_in<7>
    SLICE_X22Y17.X       Tilo                  0.608   AGNUS1/bl1/bltadat<7>
                                                       GARY1/custom_data_in<7>1
    SLICE_X12Y18.BY      net (fanout=84)       2.873   custom_data_in<7>
    SLICE_X12Y18.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<7>
                                                       AGNUS1/bl1/bltafwm_7
    -------------------------------------------------  ---------------------------
    Total                                     13.967ns (3.338ns logic, 10.629ns route)
                                                       (23.9% logic, 76.1% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_6 (SLICE_X8Y14.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  986.876ns (requirement - data path)
  Source:               cpu_data<6> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_6 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      13.124ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<6> to AGNUS1/bl1/bltalwm_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P161.I               Tiopi                 1.918   cpu_data<6>
                                                       cpu_data<6>
                                                       cpu_data_6_IOBUF/IBUF
    SLICE_X27Y24.G4      net (fanout=19)       6.451   N955
    SLICE_X27Y24.Y       Tilo                  0.551   DENISE1/sprm0/sps5/armed
                                                       gary_cpu_data_in<6>1
    SLICE_X19Y15.F1      net (fanout=4)        2.147   gary_cpu_data_in<6>
    SLICE_X19Y15.X       Tilo                  0.551   AGNUS1/bl1/bltadat<6>
                                                       GARY1/custom_data_in<6>1
    SLICE_X8Y14.BY       net (fanout=91)       1.245   custom_data_in<6>
    SLICE_X8Y14.CLK      Tdick                 0.261   AGNUS1/bl1/bltalwm<6>
                                                       AGNUS1/bl1/bltalwm_6
    -------------------------------------------------  ---------------------------
    Total                                     13.124ns (3.281ns logic, 9.843ns route)
                                                       (25.0% logic, 75.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_11 (SLICE_X3Y12.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  986.945ns (requirement - data path)
  Source:               cpu_data<11> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_11 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      13.055ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<11> to AGNUS1/bl1/bltalwm_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P144.I               Tiopi                 1.918   cpu_data<11>
                                                       cpu_data<11>
                                                       cpu_data_11_IOBUF/IBUF
    SLICE_X23Y21.G4      net (fanout=21)       3.966   N950
    SLICE_X23Y21.Y       Tilo                  0.551   DENISE1/sprm0/sps4/datlb<13>
                                                       gary_cpu_data_in<11>1
    SLICE_X22Y18.F1      net (fanout=3)        0.618   gary_cpu_data_in<11>
    SLICE_X22Y18.X       Tilo                  0.608   AGNUS1/bl1/height<11>
                                                       GARY1/custom_data_in<11>1
    SLICE_X3Y12.BY       net (fanout=72)       5.133   custom_data_in<11>
    SLICE_X3Y12.CLK      Tdick                 0.261   AGNUS1/bl1/bltalwm<11>
                                                       AGNUS1/bl1/bltalwm_11
    -------------------------------------------------  ---------------------------
    Total                                     13.055ns (3.338ns logic, 9.717ns route)
                                                       (25.6% logic, 74.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_7 (SLICE_X7Y17.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  987.098ns (requirement - data path)
  Source:               cpu_data<7> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_7 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      12.902ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<7> to AGNUS1/bl1/bltalwm_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P155.I               Tiopi                 1.918   cpu_data<7>
                                                       cpu_data<7>
                                                       cpu_data_7_IOBUF/IBUF
    SLICE_X27Y21.G2      net (fanout=22)       5.626   N954
    SLICE_X27Y21.Y       Tilo                  0.551   MIA1/magic_r_w<12>
                                                       gary_cpu_data_in<7>1
    SLICE_X22Y17.F2      net (fanout=5)        2.130   gary_cpu_data_in<7>
    SLICE_X22Y17.X       Tilo                  0.608   AGNUS1/bl1/bltadat<7>
                                                       GARY1/custom_data_in<7>1
    SLICE_X7Y17.BX       net (fanout=84)       1.866   custom_data_in<7>
    SLICE_X7Y17.CLK      Tdick                 0.203   AGNUS1/bl1/bltalwm<7>
                                                       AGNUS1/bl1/bltalwm_7
    -------------------------------------------------  ---------------------------
    Total                                     12.902ns (3.280ns logic, 9.622ns route)
                                                       (25.4% logic, 74.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_4 (SLICE_X16Y15.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  987.148ns (requirement - data path)
  Source:               cpu_data<4> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_4 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      12.852ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<4> to AGNUS1/bl1/bltafwm_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P166.I               Tiopi                 1.918   cpu_data<4>
                                                       cpu_data<4>
                                                       cpu_data_4_IOBUF/IBUF
    SLICE_X22Y24.F1      net (fanout=19)       5.022   N957
    SLICE_X22Y24.X       Tilo                  0.608   _l_data_1
                                                       gary_cpu_data_in<4>1
    SLICE_X17Y12.G4      net (fanout=6)        1.224   gary_cpu_data_in<4>
    SLICE_X17Y12.Y       Tilo                  0.551   AGNUS1/bl1/bltadat<4>
                                                       GARY1/custom_data_in<4>1
    SLICE_X16Y15.BY      net (fanout=93)       3.268   custom_data_in<4>
    SLICE_X16Y15.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<4>
                                                       AGNUS1/bl1/bltafwm_4
    -------------------------------------------------  ---------------------------
    Total                                     12.852ns (3.338ns logic, 9.514ns route)
                                                       (26.0% logic, 74.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_8 (SLICE_X6Y12.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  987.327ns (requirement - data path)
  Source:               cpu_data<8> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_8 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      12.673ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<8> to AGNUS1/bl1/bltafwm_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P152.I               Tiopi                 1.918   cpu_data<8>
                                                       cpu_data<8>
                                                       cpu_data_8_IOBUF/IBUF
    SLICE_X23Y17.F3      net (fanout=22)       5.881   N953
    SLICE_X23Y17.X       Tilo                  0.551   DENISE1/sprm0/sps2/datlb<14>
                                                       gary_cpu_data_in<8>1
    SLICE_X11Y14.F1      net (fanout=3)        1.054   gary_cpu_data_in<8>
    SLICE_X11Y14.X       Tilo                  0.551   AGNUS1/bl1/bltadat<8>
                                                       GARY1/custom_data_in<8>1
    SLICE_X6Y12.BY       net (fanout=72)       2.457   custom_data_in<8>
    SLICE_X6Y12.CLK      Tdick                 0.261   AGNUS1/bl1/bltafwm<8>
                                                       AGNUS1/bl1/bltafwm_8
    -------------------------------------------------  ---------------------------
    Total                                     12.673ns (3.281ns logic, 9.392ns route)
                                                       (25.9% logic, 74.1% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_5 (SLICE_X8Y13.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  987.498ns (requirement - data path)
  Source:               cpu_data<5> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_5 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      12.502ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<5> to AGNUS1/bl1/bltalwm_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P165.I               Tiopi                 1.918   cpu_data<5>
                                                       cpu_data<5>
                                                       cpu_data_5_IOBUF/IBUF
    SLICE_X22Y24.G4      net (fanout=19)       4.881   N956
    SLICE_X22Y24.Y       Tilo                  0.608   _l_data_1
                                                       gary_cpu_data_in<5>1
    SLICE_X17Y16.F1      net (fanout=4)        1.449   gary_cpu_data_in<5>
    SLICE_X17Y16.X       Tilo                  0.551   AGNUS1/bl1/bltadat<5>
                                                       GARY1/custom_data_in<5>1
    SLICE_X8Y13.BY       net (fanout=89)       2.834   custom_data_in<5>
    SLICE_X8Y13.CLK      Tdick                 0.261   AGNUS1/bl1/bltalwm<5>
                                                       AGNUS1/bl1/bltalwm_5
    -------------------------------------------------  ---------------------------
    Total                                     12.502ns (3.338ns logic, 9.164ns route)
                                                       (26.7% logic, 73.3% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_0 (SLICE_X10Y14.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  987.587ns (requirement - data path)
  Source:               cpu_data<0> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_0 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      12.413ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<0> to AGNUS1/bl1/bltafwm_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P150.I               Tiopi                 1.918   cpu_data<0>
                                                       cpu_data<0>
                                                       cpu_data_0_IOBUF/IBUF
    SLICE_X17Y20.F1      net (fanout=21)       4.976   N961
    SLICE_X17Y20.X       Tilo                  0.551   gary_cpu_data_in<0>
                                                       gary_cpu_data_in<0>1
    SLICE_X17Y13.G4      net (fanout=3)        1.992   gary_cpu_data_in<0>
    SLICE_X17Y13.Y       Tilo                  0.551   AGNUS1/bl1/bltadat<0>
                                                       GARY1/custom_data_in<0>2
    SLICE_X10Y14.BX      net (fanout=92)       2.222   custom_data_in<0>
    SLICE_X10Y14.CLK     Tdick                 0.203   AGNUS1/bl1/bltafwm<0>
                                                       AGNUS1/bl1/bltafwm_0
    -------------------------------------------------  ---------------------------
    Total                                     12.413ns (3.223ns logic, 9.190ns route)
                                                       (26.0% logic, 74.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_11 (SLICE_X1Y12.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  987.663ns (requirement - data path)
  Source:               cpu_data<11> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_11 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      12.337ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<11> to AGNUS1/bl1/bltafwm_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P144.I               Tiopi                 1.918   cpu_data<11>
                                                       cpu_data<11>
                                                       cpu_data_11_IOBUF/IBUF
    SLICE_X23Y21.G4      net (fanout=21)       3.966   N950
    SLICE_X23Y21.Y       Tilo                  0.551   DENISE1/sprm0/sps4/datlb<13>
                                                       gary_cpu_data_in<11>1
    SLICE_X22Y18.F1      net (fanout=3)        0.618   gary_cpu_data_in<11>
    SLICE_X22Y18.X       Tilo                  0.608   AGNUS1/bl1/height<11>
                                                       GARY1/custom_data_in<11>1
    SLICE_X1Y12.BY       net (fanout=72)       4.415   custom_data_in<11>
    SLICE_X1Y12.CLK      Tdick                 0.261   AGNUS1/bl1/bltafwm<11>
                                                       AGNUS1/bl1/bltafwm_11
    -------------------------------------------------  ---------------------------
    Total                                     12.337ns (3.338ns logic, 8.999ns route)
                                                       (27.1% logic, 72.9% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_2 (SLICE_X12Y20.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.118ns (requirement - data path)
  Source:               cpu_data<2> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_2 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.882ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<2> to AGNUS1/bl1/bltalwm_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P156.I               Tiopi                 1.918   cpu_data<2>
                                                       cpu_data<2>
                                                       cpu_data_2_IOBUF/IBUF
    SLICE_X20Y25.F4      net (fanout=20)       5.442   N959
    SLICE_X20Y25.X       Tilo                  0.608   DENISE1/sprm0/sps5/shiftb<13>
                                                       gary_cpu_data_in<2>1
    SLICE_X23Y25.F3      net (fanout=3)        0.760   gary_cpu_data_in<2>
    SLICE_X23Y25.X       Tilo                  0.551   AGNUS1/bl1/bltadat<2>
                                                       GARY1/custom_data_in<2>1
    SLICE_X12Y20.BY      net (fanout=99)       2.342   custom_data_in<2>
    SLICE_X12Y20.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<2>
                                                       AGNUS1/bl1/bltalwm_2
    -------------------------------------------------  ---------------------------
    Total                                     11.882ns (3.338ns logic, 8.544ns route)
                                                       (28.1% logic, 71.9% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_13 (SLICE_X1Y21.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.160ns (requirement - data path)
  Source:               cpu_data<13> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_13 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.840ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<13> to AGNUS1/bl1/bltalwm_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P139.I               Tiopi                 1.918   cpu_data<13>
                                                       cpu_data<13>
                                                       cpu_data_13_IOBUF/IBUF
    SLICE_X19Y23.F3      net (fanout=21)       4.043   N948
    SLICE_X19Y23.X       Tilo                  0.551   gary_cpu_data_in<13>
                                                       gary_cpu_data_in<13>1
    SLICE_X22Y20.F1      net (fanout=4)        1.259   gary_cpu_data_in<13>
    SLICE_X22Y20.X       Tilo                  0.608   AGNUS1/bl1/height<13>
                                                       GARY1/custom_data_in<13>1
    SLICE_X1Y21.BY       net (fanout=70)       3.200   custom_data_in<13>
    SLICE_X1Y21.CLK      Tdick                 0.261   AGNUS1/bl1/bltalwm<12>
                                                       AGNUS1/bl1/bltalwm_13
    -------------------------------------------------  ---------------------------
    Total                                     11.840ns (3.338ns logic, 8.502ns route)
                                                       (28.2% logic, 71.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_13 (SLICE_X1Y19.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.421ns (requirement - data path)
  Source:               cpu_data<13> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_13 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.579ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<13> to AGNUS1/bl1/bltafwm_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P139.I               Tiopi                 1.918   cpu_data<13>
                                                       cpu_data<13>
                                                       cpu_data_13_IOBUF/IBUF
    SLICE_X19Y23.F3      net (fanout=21)       4.043   N948
    SLICE_X19Y23.X       Tilo                  0.551   gary_cpu_data_in<13>
                                                       gary_cpu_data_in<13>1
    SLICE_X22Y20.F1      net (fanout=4)        1.259   gary_cpu_data_in<13>
    SLICE_X22Y20.X       Tilo                  0.608   AGNUS1/bl1/height<13>
                                                       GARY1/custom_data_in<13>1
    SLICE_X1Y19.BX       net (fanout=70)       2.997   custom_data_in<13>
    SLICE_X1Y19.CLK      Tdick                 0.203   AGNUS1/bl1/bltafwm<13>
                                                       AGNUS1/bl1/bltafwm_13
    -------------------------------------------------  ---------------------------
    Total                                     11.579ns (3.280ns logic, 8.299ns route)
                                                       (28.3% logic, 71.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_0 (SLICE_X12Y12.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.594ns (requirement - data path)
  Source:               cpu_data<0> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_0 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.406ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<0> to AGNUS1/bl1/bltalwm_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P150.I               Tiopi                 1.918   cpu_data<0>
                                                       cpu_data<0>
                                                       cpu_data_0_IOBUF/IBUF
    SLICE_X17Y20.F1      net (fanout=21)       4.976   N961
    SLICE_X17Y20.X       Tilo                  0.551   gary_cpu_data_in<0>
                                                       gary_cpu_data_in<0>1
    SLICE_X17Y13.G4      net (fanout=3)        1.992   gary_cpu_data_in<0>
    SLICE_X17Y13.Y       Tilo                  0.551   AGNUS1/bl1/bltadat<0>
                                                       GARY1/custom_data_in<0>2
    SLICE_X12Y12.BY      net (fanout=92)       1.157   custom_data_in<0>
    SLICE_X12Y12.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<0>
                                                       AGNUS1/bl1/bltalwm_0
    -------------------------------------------------  ---------------------------
    Total                                     11.406ns (3.281ns logic, 8.125ns route)
                                                       (28.8% logic, 71.2% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_1 (SLICE_X10Y14.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.629ns (requirement - data path)
  Source:               cpu_data<1> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_1 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.371ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<1> to AGNUS1/bl1/bltafwm_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P154.I               Tiopi                 1.918   cpu_data<1>
                                                       cpu_data<1>
                                                       cpu_data_1_IOBUF/IBUF
    SLICE_X20Y19.G2      net (fanout=21)       4.801   N960
    SLICE_X20Y19.Y       Tilo                  0.608   AGNUS1/cp1/cop2lch<18>
                                                       gary_cpu_data_in<1>1
    SLICE_X19Y12.G4      net (fanout=5)        0.881   gary_cpu_data_in<1>
    SLICE_X19Y12.Y       Tilo                  0.551   AGNUS1/bl1/bltadat<1>
                                                       GARY1/custom_data_in<1>1
    SLICE_X10Y14.BY      net (fanout=96)       2.351   custom_data_in<1>
    SLICE_X10Y14.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<0>
                                                       AGNUS1/bl1/bltafwm_1
    -------------------------------------------------  ---------------------------
    Total                                     11.371ns (3.338ns logic, 8.033ns route)
                                                       (29.4% logic, 70.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_8 (SLICE_X7Y17.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.761ns (requirement - data path)
  Source:               cpu_data<8> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_8 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.239ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<8> to AGNUS1/bl1/bltalwm_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P152.I               Tiopi                 1.918   cpu_data<8>
                                                       cpu_data<8>
                                                       cpu_data_8_IOBUF/IBUF
    SLICE_X23Y17.F3      net (fanout=22)       5.881   N953
    SLICE_X23Y17.X       Tilo                  0.551   DENISE1/sprm0/sps2/datlb<14>
                                                       gary_cpu_data_in<8>1
    SLICE_X11Y14.F1      net (fanout=3)        1.054   gary_cpu_data_in<8>
    SLICE_X11Y14.X       Tilo                  0.551   AGNUS1/bl1/bltadat<8>
                                                       GARY1/custom_data_in<8>1
    SLICE_X7Y17.BY       net (fanout=72)       1.023   custom_data_in<8>
    SLICE_X7Y17.CLK      Tdick                 0.261   AGNUS1/bl1/bltalwm<7>
                                                       AGNUS1/bl1/bltalwm_8
    -------------------------------------------------  ---------------------------
    Total                                     11.239ns (3.281ns logic, 7.958ns route)
                                                       (29.2% logic, 70.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_2 (SLICE_X10Y17.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  989.002ns (requirement - data path)
  Source:               cpu_data<2> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_2 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      10.998ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<2> to AGNUS1/bl1/bltafwm_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P156.I               Tiopi                 1.918   cpu_data<2>
                                                       cpu_data<2>
                                                       cpu_data_2_IOBUF/IBUF
    SLICE_X20Y25.F4      net (fanout=20)       5.442   N959
    SLICE_X20Y25.X       Tilo                  0.608   DENISE1/sprm0/sps5/shiftb<13>
                                                       gary_cpu_data_in<2>1
    SLICE_X23Y25.F3      net (fanout=3)        0.760   gary_cpu_data_in<2>
    SLICE_X23Y25.X       Tilo                  0.551   AGNUS1/bl1/bltadat<2>
                                                       GARY1/custom_data_in<2>1
    SLICE_X10Y17.BX      net (fanout=99)       1.516   custom_data_in<2>
    SLICE_X10Y17.CLK     Tdick                 0.203   AGNUS1/bl1/bltafwm<2>
                                                       AGNUS1/bl1/bltafwm_2
    -------------------------------------------------  ---------------------------
    Total                                     10.998ns (3.280ns logic, 7.718ns route)
                                                       (29.8% logic, 70.2% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_14 (SLICE_X1Y17.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  989.052ns (requirement - data path)
  Source:               cpu_data<14> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_14 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      10.948ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<14> to AGNUS1/bl1/bltalwm_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P137.I               Tiopi                 1.918   cpu_data<14>
                                                       cpu_data<14>
                                                       cpu_data_14_IOBUF/IBUF
    SLICE_X18Y21.F2      net (fanout=22)       3.679   N947
    SLICE_X18Y21.X       Tilo                  0.608   gary_cpu_data_in<14>
                                                       gary_cpu_data_in<14>1
    SLICE_X20Y21.F1      net (fanout=4)        1.003   gary_cpu_data_in<14>
    SLICE_X20Y21.X       Tilo                  0.608   AGNUS1/bl1/height<14>
                                                       GARY1/custom_data_in<14>1
    SLICE_X1Y17.BX       net (fanout=69)       2.929   custom_data_in<14>
    SLICE_X1Y17.CLK      Tdick                 0.203   AGNUS1/bl1/bltalwm<14>
                                                       AGNUS1/bl1/bltalwm_14
    -------------------------------------------------  ---------------------------
    Total                                     10.948ns (3.337ns logic, 7.611ns route)
                                                       (30.5% logic, 69.5% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_10 (SLICE_X2Y8.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  989.103ns (requirement - data path)
  Source:               cpu_data<10> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_10 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      10.897ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<10> to AGNUS1/bl1/bltafwm_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P147.I               Tiopi                 1.918   cpu_data<10>
                                                       cpu_data<10>
                                                       cpu_data_10_IOBUF/IBUF
    SLICE_X23Y21.F1      net (fanout=22)       4.395   N951
    SLICE_X23Y21.X       Tilo                  0.551   DENISE1/sprm0/sps4/datlb<13>
                                                       gary_cpu_data_in<10>1
    SLICE_X22Y19.F4      net (fanout=3)        0.375   gary_cpu_data_in<10>
    SLICE_X22Y19.X       Tilo                  0.608   AGNUS1/bl1/height<10>
                                                       GARY1/custom_data_in<10>1
    SLICE_X2Y8.BY        net (fanout=75)       2.789   custom_data_in<10>
    SLICE_X2Y8.CLK       Tdick                 0.261   AGNUS1/bl1/bltafwm<10>
                                                       AGNUS1/bl1/bltafwm_10
    -------------------------------------------------  ---------------------------
    Total                                     10.897ns (3.338ns logic, 7.559ns route)
                                                       (30.6% logic, 69.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_9 (SLICE_X8Y20.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  989.108ns (requirement - data path)
  Source:               cpu_data<9> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_9 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      10.892ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<9> to AGNUS1/bl1/bltafwm_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P149.I               Tiopi                 1.918   cpu_data<9>
                                                       cpu_data<9>
                                                       cpu_data_9_IOBUF/IBUF
    SLICE_X21Y19.F2      net (fanout=22)       4.824   N952
    SLICE_X21Y19.X       Tilo                  0.551   DENISE1/sprm0/sps4/shifta<13>
                                                       gary_cpu_data_in<9>1
    SLICE_X21Y20.F4      net (fanout=3)        0.360   gary_cpu_data_in<9>
    SLICE_X21Y20.X       Tilo                  0.551   AGNUS1/bl1/bltadat<9>
                                                       GARY1/custom_data_in<9>1
    SLICE_X8Y20.BY       net (fanout=73)       2.427   custom_data_in<9>
    SLICE_X8Y20.CLK      Tdick                 0.261   AGNUS1/bl1/bltafwm<9>
                                                       AGNUS1/bl1/bltafwm_9
    -------------------------------------------------  ---------------------------
    Total                                     10.892ns (3.281ns logic, 7.611ns route)
                                                       (30.1% logic, 69.9% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_3 (SLICE_X11Y19.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  989.127ns (requirement - data path)
  Source:               cpu_data<3> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_3 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      10.873ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<3> to AGNUS1/bl1/bltalwm_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P162.I               Tiopi                 1.918   cpu_data<3>
                                                       cpu_data<3>
                                                       cpu_data_3_IOBUF/IBUF
    SLICE_X17Y20.G4      net (fanout=20)       5.076   N958
    SLICE_X17Y20.Y       Tilo                  0.551   gary_cpu_data_in<0>
                                                       gary_cpu_data_in<3>1
    SLICE_X17Y25.G1      net (fanout=5)        0.995   gary_cpu_data_in<3>
    SLICE_X17Y25.Y       Tilo                  0.551   AGNUS1/bl1/bltadat<3>
                                                       GARY1/custom_data_in<3>1
    SLICE_X11Y19.BX      net (fanout=93)       1.579   custom_data_in<3>
    SLICE_X11Y19.CLK     Tdick                 0.203   AGNUS1/bl1/bltalwm<3>
                                                       AGNUS1/bl1/bltalwm_3
    -------------------------------------------------  ---------------------------
    Total                                     10.873ns (3.223ns logic, 7.650ns route)
                                                       (29.6% logic, 70.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_3 (SLICE_X10Y17.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  989.141ns (requirement - data path)
  Source:               cpu_data<3> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_3 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      10.859ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<3> to AGNUS1/bl1/bltafwm_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P162.I               Tiopi                 1.918   cpu_data<3>
                                                       cpu_data<3>
                                                       cpu_data_3_IOBUF/IBUF
    SLICE_X17Y20.G4      net (fanout=20)       5.076   N958
    SLICE_X17Y20.Y       Tilo                  0.551   gary_cpu_data_in<0>
                                                       gary_cpu_data_in<3>1
    SLICE_X17Y25.G1      net (fanout=5)        0.995   gary_cpu_data_in<3>
    SLICE_X17Y25.Y       Tilo                  0.551   AGNUS1/bl1/bltadat<3>
                                                       GARY1/custom_data_in<3>1
    SLICE_X10Y17.BY      net (fanout=93)       1.507   custom_data_in<3>
    SLICE_X10Y17.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<2>
                                                       AGNUS1/bl1/bltafwm_3
    -------------------------------------------------  ---------------------------
    Total                                     10.859ns (3.281ns logic, 7.578ns route)
                                                       (30.2% logic, 69.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_5 (SLICE_X13Y17.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  989.341ns (requirement - data path)
  Source:               cpu_data<5> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_5 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      10.659ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<5> to AGNUS1/bl1/bltafwm_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P165.I               Tiopi                 1.918   cpu_data<5>
                                                       cpu_data<5>
                                                       cpu_data_5_IOBUF/IBUF
    SLICE_X22Y24.G4      net (fanout=19)       4.881   N956
    SLICE_X22Y24.Y       Tilo                  0.608   _l_data_1
                                                       gary_cpu_data_in<5>1
    SLICE_X17Y16.F1      net (fanout=4)        1.449   gary_cpu_data_in<5>
    SLICE_X17Y16.X       Tilo                  0.551   AGNUS1/bl1/bltadat<5>
                                                       GARY1/custom_data_in<5>1
    SLICE_X13Y17.BX      net (fanout=89)       1.049   custom_data_in<5>
    SLICE_X13Y17.CLK     Tdick                 0.203   AGNUS1/bl1/bltafwm<5>
                                                       AGNUS1/bl1/bltafwm_5
    -------------------------------------------------  ---------------------------
    Total                                     10.659ns (3.280ns logic, 7.379ns route)
                                                       (30.8% logic, 69.2% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_4 (SLICE_X10Y12.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  989.349ns (requirement - data path)
  Source:               cpu_data<4> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_4 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      10.651ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<4> to AGNUS1/bl1/bltalwm_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P166.I               Tiopi                 1.918   cpu_data<4>
                                                       cpu_data<4>
                                                       cpu_data_4_IOBUF/IBUF
    SLICE_X22Y24.F1      net (fanout=19)       5.022   N957
    SLICE_X22Y24.X       Tilo                  0.608   _l_data_1
                                                       gary_cpu_data_in<4>1
    SLICE_X17Y12.G4      net (fanout=6)        1.224   gary_cpu_data_in<4>
    SLICE_X17Y12.Y       Tilo                  0.551   AGNUS1/bl1/bltadat<4>
                                                       GARY1/custom_data_in<4>1
    SLICE_X10Y12.BY      net (fanout=93)       1.067   custom_data_in<4>
    SLICE_X10Y12.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<1>
                                                       AGNUS1/bl1/bltalwm_4
    -------------------------------------------------  ---------------------------
    Total                                     10.651ns (3.338ns logic, 7.313ns route)
                                                       (31.3% logic, 68.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_10 (SLICE_X2Y10.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  989.444ns (requirement - data path)
  Source:               cpu_data<10> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_10 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      10.556ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<10> to AGNUS1/bl1/bltalwm_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P147.I               Tiopi                 1.918   cpu_data<10>
                                                       cpu_data<10>
                                                       cpu_data_10_IOBUF/IBUF
    SLICE_X23Y21.F1      net (fanout=22)       4.395   N951
    SLICE_X23Y21.X       Tilo                  0.551   DENISE1/sprm0/sps4/datlb<13>
                                                       gary_cpu_data_in<10>1
    SLICE_X22Y19.F4      net (fanout=3)        0.375   gary_cpu_data_in<10>
    SLICE_X22Y19.X       Tilo                  0.608   AGNUS1/bl1/height<10>
                                                       GARY1/custom_data_in<10>1
    SLICE_X2Y10.BY       net (fanout=75)       2.448   custom_data_in<10>
    SLICE_X2Y10.CLK      Tdick                 0.261   AGNUS1/bl1/bltalwm<10>
                                                       AGNUS1/bl1/bltalwm_10
    -------------------------------------------------  ---------------------------
    Total                                     10.556ns (3.338ns logic, 7.218ns route)
                                                       (31.6% logic, 68.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_1 (SLICE_X10Y12.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  989.767ns (requirement - data path)
  Source:               cpu_data<1> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_1 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      10.233ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<1> to AGNUS1/bl1/bltalwm_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P154.I               Tiopi                 1.918   cpu_data<1>
                                                       cpu_data<1>
                                                       cpu_data_1_IOBUF/IBUF
    SLICE_X20Y19.G2      net (fanout=21)       4.801   N960
    SLICE_X20Y19.Y       Tilo                  0.608   AGNUS1/cp1/cop2lch<18>
                                                       gary_cpu_data_in<1>1
    SLICE_X19Y12.G4      net (fanout=5)        0.881   gary_cpu_data_in<1>
    SLICE_X19Y12.Y       Tilo                  0.551   AGNUS1/bl1/bltadat<1>
                                                       GARY1/custom_data_in<1>1
    SLICE_X10Y12.BX      net (fanout=96)       1.271   custom_data_in<1>
    SLICE_X10Y12.CLK     Tdick                 0.203   AGNUS1/bl1/bltalwm<1>
                                                       AGNUS1/bl1/bltalwm_1
    -------------------------------------------------  ---------------------------
    Total                                     10.233ns (3.280ns logic, 6.953ns route)
                                                       (32.1% logic, 67.9% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_14 (SLICE_X1Y19.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  989.801ns (requirement - data path)
  Source:               cpu_data<14> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_14 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      10.199ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<14> to AGNUS1/bl1/bltafwm_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P137.I               Tiopi                 1.918   cpu_data<14>
                                                       cpu_data<14>
                                                       cpu_data_14_IOBUF/IBUF
    SLICE_X18Y21.F2      net (fanout=22)       3.679   N947
    SLICE_X18Y21.X       Tilo                  0.608   gary_cpu_data_in<14>
                                                       gary_cpu_data_in<14>1
    SLICE_X20Y21.F1      net (fanout=4)        1.003   gary_cpu_data_in<14>
    SLICE_X20Y21.X       Tilo                  0.608   AGNUS1/bl1/height<14>
                                                       GARY1/custom_data_in<14>1
    SLICE_X1Y19.BY       net (fanout=69)       2.122   custom_data_in<14>
    SLICE_X1Y19.CLK      Tdick                 0.261   AGNUS1/bl1/bltafwm<13>
                                                       AGNUS1/bl1/bltafwm_14
    -------------------------------------------------  ---------------------------
    Total                                     10.199ns (3.395ns logic, 6.804ns route)
                                                       (33.3% logic, 66.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_9 (SLICE_X11Y19.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  989.972ns (requirement - data path)
  Source:               cpu_data<9> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_9 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      10.028ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<9> to AGNUS1/bl1/bltalwm_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P149.I               Tiopi                 1.918   cpu_data<9>
                                                       cpu_data<9>
                                                       cpu_data_9_IOBUF/IBUF
    SLICE_X21Y19.F2      net (fanout=22)       4.824   N952
    SLICE_X21Y19.X       Tilo                  0.551   DENISE1/sprm0/sps4/shifta<13>
                                                       gary_cpu_data_in<9>1
    SLICE_X21Y20.F4      net (fanout=3)        0.360   gary_cpu_data_in<9>
    SLICE_X21Y20.X       Tilo                  0.551   AGNUS1/bl1/bltadat<9>
                                                       GARY1/custom_data_in<9>1
    SLICE_X11Y19.BY      net (fanout=73)       1.563   custom_data_in<9>
    SLICE_X11Y19.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<3>
                                                       AGNUS1/bl1/bltalwm_9
    -------------------------------------------------  ---------------------------
    Total                                     10.028ns (3.281ns logic, 6.747ns route)
                                                       (32.7% logic, 67.3% route)

--------------------------------------------------------------------------------

Fastest Paths: TS_R3_CUSTOM_DATA = MAXDELAY FROM TIMEGRP "CPU_DATA" TO TIMEGRP "R3_CUSTOM_MASKS" 1000 ns DATAPATHONLY;
--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_9 (SLICE_X11Y19.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      7.572ns (data path)
  Source:               cpu_data<9> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_9 (FF)
  Requirement:          0.000ns
  Data Path Delay:      7.572ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<9> to AGNUS1/bl1/bltalwm_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P149.I               Tiopi                 1.530   cpu_data<9>
                                                       cpu_data<9>
                                                       cpu_data_9_IOBUF/IBUF
    SLICE_X21Y19.F2      net (fanout=22)       3.859   N952
    SLICE_X21Y19.X       Tilo                  0.441   DENISE1/sprm0/sps4/shifta<13>
                                                       gary_cpu_data_in<9>1
    SLICE_X21Y20.F4      net (fanout=3)        0.288   gary_cpu_data_in<9>
    SLICE_X21Y20.X       Tilo                  0.441   AGNUS1/bl1/bltadat<9>
                                                       GARY1/custom_data_in<9>1
    SLICE_X11Y19.BY      net (fanout=73)       1.250   custom_data_in<9>
    SLICE_X11Y19.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<3>
                                                       AGNUS1/bl1/bltalwm_9
    -------------------------------------------------  ---------------------------
    Total                                      7.572ns (2.175ns logic, 5.397ns route)
                                                       (28.7% logic, 71.3% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_14 (SLICE_X1Y19.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      7.709ns (data path)
  Source:               cpu_data<14> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_14 (FF)
  Requirement:          0.000ns
  Data Path Delay:      7.709ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<14> to AGNUS1/bl1/bltafwm_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P137.I               Tiopi                 1.530   cpu_data<14>
                                                       cpu_data<14>
                                                       cpu_data_14_IOBUF/IBUF
    SLICE_X18Y21.F2      net (fanout=22)       2.944   N947
    SLICE_X18Y21.X       Tilo                  0.486   gary_cpu_data_in<14>
                                                       gary_cpu_data_in<14>1
    SLICE_X20Y21.F1      net (fanout=4)        0.803   gary_cpu_data_in<14>
    SLICE_X20Y21.X       Tilo                  0.486   AGNUS1/bl1/height<14>
                                                       GARY1/custom_data_in<14>1
    SLICE_X1Y19.BY       net (fanout=69)       1.697   custom_data_in<14>
    SLICE_X1Y19.CLK      Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<13>
                                                       AGNUS1/bl1/bltafwm_14
    -------------------------------------------------  ---------------------------
    Total                                      7.709ns (2.265ns logic, 5.444ns route)
                                                       (29.4% logic, 70.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_1 (SLICE_X10Y12.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      7.736ns (data path)
  Source:               cpu_data<1> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      7.736ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<1> to AGNUS1/bl1/bltalwm_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P154.I               Tiopi                 1.530   cpu_data<1>
                                                       cpu_data<1>
                                                       cpu_data_1_IOBUF/IBUF
    SLICE_X20Y19.G2      net (fanout=21)       3.841   N960
    SLICE_X20Y19.Y       Tilo                  0.486   AGNUS1/cp1/cop2lch<18>
                                                       gary_cpu_data_in<1>1
    SLICE_X19Y12.G4      net (fanout=5)        0.704   gary_cpu_data_in<1>
    SLICE_X19Y12.Y       Tilo                  0.441   AGNUS1/bl1/bltadat<1>
                                                       GARY1/custom_data_in<1>1
    SLICE_X10Y12.BX      net (fanout=96)       1.017   custom_data_in<1>
    SLICE_X10Y12.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltalwm<1>
                                                       AGNUS1/bl1/bltalwm_1
    -------------------------------------------------  ---------------------------
    Total                                      7.736ns (2.174ns logic, 5.562ns route)
                                                       (28.1% logic, 71.9% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_10 (SLICE_X2Y10.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      7.995ns (data path)
  Source:               cpu_data<10> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_10 (FF)
  Requirement:          0.000ns
  Data Path Delay:      7.995ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<10> to AGNUS1/bl1/bltalwm_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P147.I               Tiopi                 1.530   cpu_data<10>
                                                       cpu_data<10>
                                                       cpu_data_10_IOBUF/IBUF
    SLICE_X23Y21.F1      net (fanout=22)       3.516   N951
    SLICE_X23Y21.X       Tilo                  0.441   DENISE1/sprm0/sps4/datlb<13>
                                                       gary_cpu_data_in<10>1
    SLICE_X22Y19.F4      net (fanout=3)        0.300   gary_cpu_data_in<10>
    SLICE_X22Y19.X       Tilo                  0.486   AGNUS1/bl1/height<10>
                                                       GARY1/custom_data_in<10>1
    SLICE_X2Y10.BY       net (fanout=75)       1.959   custom_data_in<10>
    SLICE_X2Y10.CLK      Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<10>
                                                       AGNUS1/bl1/bltalwm_10
    -------------------------------------------------  ---------------------------
    Total                                      7.995ns (2.220ns logic, 5.775ns route)
                                                       (27.8% logic, 72.2% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_4 (SLICE_X10Y12.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.070ns (data path)
  Source:               cpu_data<4> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.070ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<4> to AGNUS1/bl1/bltalwm_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P166.I               Tiopi                 1.530   cpu_data<4>
                                                       cpu_data<4>
                                                       cpu_data_4_IOBUF/IBUF
    SLICE_X22Y24.F1      net (fanout=19)       4.017   N957
    SLICE_X22Y24.X       Tilo                  0.486   _l_data_1
                                                       gary_cpu_data_in<4>1
    SLICE_X17Y12.G4      net (fanout=6)        0.979   gary_cpu_data_in<4>
    SLICE_X17Y12.Y       Tilo                  0.441   AGNUS1/bl1/bltadat<4>
                                                       GARY1/custom_data_in<4>1
    SLICE_X10Y12.BY      net (fanout=93)       0.854   custom_data_in<4>
    SLICE_X10Y12.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<1>
                                                       AGNUS1/bl1/bltalwm_4
    -------------------------------------------------  ---------------------------
    Total                                      8.070ns (2.220ns logic, 5.850ns route)
                                                       (27.5% logic, 72.5% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_5 (SLICE_X13Y17.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.077ns (data path)
  Source:               cpu_data<5> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_5 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.077ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<5> to AGNUS1/bl1/bltafwm_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P165.I               Tiopi                 1.530   cpu_data<5>
                                                       cpu_data<5>
                                                       cpu_data_5_IOBUF/IBUF
    SLICE_X22Y24.G4      net (fanout=19)       3.905   N956
    SLICE_X22Y24.Y       Tilo                  0.486   _l_data_1
                                                       gary_cpu_data_in<5>1
    SLICE_X17Y16.F1      net (fanout=4)        1.159   gary_cpu_data_in<5>
    SLICE_X17Y16.X       Tilo                  0.441   AGNUS1/bl1/bltadat<5>
                                                       GARY1/custom_data_in<5>1
    SLICE_X13Y17.BX      net (fanout=89)       0.839   custom_data_in<5>
    SLICE_X13Y17.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltafwm<5>
                                                       AGNUS1/bl1/bltafwm_5
    -------------------------------------------------  ---------------------------
    Total                                      8.077ns (2.174ns logic, 5.903ns route)
                                                       (26.9% logic, 73.1% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_3 (SLICE_X10Y17.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.238ns (data path)
  Source:               cpu_data<3> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.238ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<3> to AGNUS1/bl1/bltafwm_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P162.I               Tiopi                 1.530   cpu_data<3>
                                                       cpu_data<3>
                                                       cpu_data_3_IOBUF/IBUF
    SLICE_X17Y20.G4      net (fanout=20)       4.061   N958
    SLICE_X17Y20.Y       Tilo                  0.441   gary_cpu_data_in<0>
                                                       gary_cpu_data_in<3>1
    SLICE_X17Y25.G1      net (fanout=5)        0.796   gary_cpu_data_in<3>
    SLICE_X17Y25.Y       Tilo                  0.441   AGNUS1/bl1/bltadat<3>
                                                       GARY1/custom_data_in<3>1
    SLICE_X10Y17.BY      net (fanout=93)       1.206   custom_data_in<3>
    SLICE_X10Y17.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<2>
                                                       AGNUS1/bl1/bltafwm_3
    -------------------------------------------------  ---------------------------
    Total                                      8.238ns (2.175ns logic, 6.063ns route)
                                                       (26.4% logic, 73.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_9 (SLICE_X8Y20.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.263ns (data path)
  Source:               cpu_data<9> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_9 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.263ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<9> to AGNUS1/bl1/bltafwm_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P149.I               Tiopi                 1.530   cpu_data<9>
                                                       cpu_data<9>
                                                       cpu_data_9_IOBUF/IBUF
    SLICE_X21Y19.F2      net (fanout=22)       3.859   N952
    SLICE_X21Y19.X       Tilo                  0.441   DENISE1/sprm0/sps4/shifta<13>
                                                       gary_cpu_data_in<9>1
    SLICE_X21Y20.F4      net (fanout=3)        0.288   gary_cpu_data_in<9>
    SLICE_X21Y20.X       Tilo                  0.441   AGNUS1/bl1/bltadat<9>
                                                       GARY1/custom_data_in<9>1
    SLICE_X8Y20.BY       net (fanout=73)       1.941   custom_data_in<9>
    SLICE_X8Y20.CLK      Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<9>
                                                       AGNUS1/bl1/bltafwm_9
    -------------------------------------------------  ---------------------------
    Total                                      8.263ns (2.175ns logic, 6.088ns route)
                                                       (26.3% logic, 73.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_10 (SLICE_X2Y8.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.267ns (data path)
  Source:               cpu_data<10> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_10 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.267ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<10> to AGNUS1/bl1/bltafwm_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P147.I               Tiopi                 1.530   cpu_data<10>
                                                       cpu_data<10>
                                                       cpu_data_10_IOBUF/IBUF
    SLICE_X23Y21.F1      net (fanout=22)       3.516   N951
    SLICE_X23Y21.X       Tilo                  0.441   DENISE1/sprm0/sps4/datlb<13>
                                                       gary_cpu_data_in<10>1
    SLICE_X22Y19.F4      net (fanout=3)        0.300   gary_cpu_data_in<10>
    SLICE_X22Y19.X       Tilo                  0.486   AGNUS1/bl1/height<10>
                                                       GARY1/custom_data_in<10>1
    SLICE_X2Y8.BY        net (fanout=75)       2.231   custom_data_in<10>
    SLICE_X2Y8.CLK       Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<10>
                                                       AGNUS1/bl1/bltafwm_10
    -------------------------------------------------  ---------------------------
    Total                                      8.267ns (2.220ns logic, 6.047ns route)
                                                       (26.9% logic, 73.1% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_3 (SLICE_X11Y19.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.249ns (data path)
  Source:               cpu_data<3> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.249ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<3> to AGNUS1/bl1/bltalwm_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P162.I               Tiopi                 1.530   cpu_data<3>
                                                       cpu_data<3>
                                                       cpu_data_3_IOBUF/IBUF
    SLICE_X17Y20.G4      net (fanout=20)       4.061   N958
    SLICE_X17Y20.Y       Tilo                  0.441   gary_cpu_data_in<0>
                                                       gary_cpu_data_in<3>1
    SLICE_X17Y25.G1      net (fanout=5)        0.796   gary_cpu_data_in<3>
    SLICE_X17Y25.Y       Tilo                  0.441   AGNUS1/bl1/bltadat<3>
                                                       GARY1/custom_data_in<3>1
    SLICE_X11Y19.BX      net (fanout=93)       1.263   custom_data_in<3>
    SLICE_X11Y19.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltalwm<3>
                                                       AGNUS1/bl1/bltalwm_3
    -------------------------------------------------  ---------------------------
    Total                                      8.249ns (2.129ns logic, 6.120ns route)
                                                       (25.8% logic, 74.2% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_14 (SLICE_X1Y17.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.309ns (data path)
  Source:               cpu_data<14> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_14 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.309ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<14> to AGNUS1/bl1/bltalwm_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P137.I               Tiopi                 1.530   cpu_data<14>
                                                       cpu_data<14>
                                                       cpu_data_14_IOBUF/IBUF
    SLICE_X18Y21.F2      net (fanout=22)       2.944   N947
    SLICE_X18Y21.X       Tilo                  0.486   gary_cpu_data_in<14>
                                                       gary_cpu_data_in<14>1
    SLICE_X20Y21.F1      net (fanout=4)        0.803   gary_cpu_data_in<14>
    SLICE_X20Y21.X       Tilo                  0.486   AGNUS1/bl1/height<14>
                                                       GARY1/custom_data_in<14>1
    SLICE_X1Y17.BX       net (fanout=69)       2.343   custom_data_in<14>
    SLICE_X1Y17.CLK      Tckdi       (-Th)     0.283   AGNUS1/bl1/bltalwm<14>
                                                       AGNUS1/bl1/bltalwm_14
    -------------------------------------------------  ---------------------------
    Total                                      8.309ns (2.219ns logic, 6.090ns route)
                                                       (26.7% logic, 73.3% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_2 (SLICE_X10Y17.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.348ns (data path)
  Source:               cpu_data<2> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.348ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<2> to AGNUS1/bl1/bltafwm_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P156.I               Tiopi                 1.530   cpu_data<2>
                                                       cpu_data<2>
                                                       cpu_data_2_IOBUF/IBUF
    SLICE_X20Y25.F4      net (fanout=20)       4.353   N959
    SLICE_X20Y25.X       Tilo                  0.486   DENISE1/sprm0/sps5/shiftb<13>
                                                       gary_cpu_data_in<2>1
    SLICE_X23Y25.F3      net (fanout=3)        0.608   gary_cpu_data_in<2>
    SLICE_X23Y25.X       Tilo                  0.441   AGNUS1/bl1/bltadat<2>
                                                       GARY1/custom_data_in<2>1
    SLICE_X10Y17.BX      net (fanout=99)       1.213   custom_data_in<2>
    SLICE_X10Y17.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltafwm<2>
                                                       AGNUS1/bl1/bltafwm_2
    -------------------------------------------------  ---------------------------
    Total                                      8.348ns (2.174ns logic, 6.174ns route)
                                                       (26.0% logic, 74.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_8 (SLICE_X7Y17.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.541ns (data path)
  Source:               cpu_data<8> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.541ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<8> to AGNUS1/bl1/bltalwm_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P152.I               Tiopi                 1.530   cpu_data<8>
                                                       cpu_data<8>
                                                       cpu_data_8_IOBUF/IBUF
    SLICE_X23Y17.F3      net (fanout=22)       4.705   N953
    SLICE_X23Y17.X       Tilo                  0.441   DENISE1/sprm0/sps2/datlb<14>
                                                       gary_cpu_data_in<8>1
    SLICE_X11Y14.F1      net (fanout=3)        0.843   gary_cpu_data_in<8>
    SLICE_X11Y14.X       Tilo                  0.441   AGNUS1/bl1/bltadat<8>
                                                       GARY1/custom_data_in<8>1
    SLICE_X7Y17.BY       net (fanout=72)       0.818   custom_data_in<8>
    SLICE_X7Y17.CLK      Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<7>
                                                       AGNUS1/bl1/bltalwm_8
    -------------------------------------------------  ---------------------------
    Total                                      8.541ns (2.175ns logic, 6.366ns route)
                                                       (25.5% logic, 74.5% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_1 (SLICE_X10Y14.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.646ns (data path)
  Source:               cpu_data<1> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.646ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<1> to AGNUS1/bl1/bltafwm_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P154.I               Tiopi                 1.530   cpu_data<1>
                                                       cpu_data<1>
                                                       cpu_data_1_IOBUF/IBUF
    SLICE_X20Y19.G2      net (fanout=21)       3.841   N960
    SLICE_X20Y19.Y       Tilo                  0.486   AGNUS1/cp1/cop2lch<18>
                                                       gary_cpu_data_in<1>1
    SLICE_X19Y12.G4      net (fanout=5)        0.704   gary_cpu_data_in<1>
    SLICE_X19Y12.Y       Tilo                  0.441   AGNUS1/bl1/bltadat<1>
                                                       GARY1/custom_data_in<1>1
    SLICE_X10Y14.BY      net (fanout=96)       1.881   custom_data_in<1>
    SLICE_X10Y14.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<0>
                                                       AGNUS1/bl1/bltafwm_1
    -------------------------------------------------  ---------------------------
    Total                                      8.646ns (2.220ns logic, 6.426ns route)
                                                       (25.7% logic, 74.3% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_0 (SLICE_X12Y12.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.676ns (data path)
  Source:               cpu_data<0> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.676ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<0> to AGNUS1/bl1/bltalwm_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P150.I               Tiopi                 1.530   cpu_data<0>
                                                       cpu_data<0>
                                                       cpu_data_0_IOBUF/IBUF
    SLICE_X17Y20.F1      net (fanout=21)       3.981   N961
    SLICE_X17Y20.X       Tilo                  0.441   gary_cpu_data_in<0>
                                                       gary_cpu_data_in<0>1
    SLICE_X17Y13.G4      net (fanout=3)        1.594   gary_cpu_data_in<0>
    SLICE_X17Y13.Y       Tilo                  0.441   AGNUS1/bl1/bltadat<0>
                                                       GARY1/custom_data_in<0>2
    SLICE_X12Y12.BY      net (fanout=92)       0.926   custom_data_in<0>
    SLICE_X12Y12.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<0>
                                                       AGNUS1/bl1/bltalwm_0
    -------------------------------------------------  ---------------------------
    Total                                      8.676ns (2.175ns logic, 6.501ns route)
                                                       (25.1% logic, 74.9% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_13 (SLICE_X1Y19.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.813ns (data path)
  Source:               cpu_data<13> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_13 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.813ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<13> to AGNUS1/bl1/bltafwm_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P139.I               Tiopi                 1.530   cpu_data<13>
                                                       cpu_data<13>
                                                       cpu_data_13_IOBUF/IBUF
    SLICE_X19Y23.F3      net (fanout=21)       3.234   N948
    SLICE_X19Y23.X       Tilo                  0.441   gary_cpu_data_in<13>
                                                       gary_cpu_data_in<13>1
    SLICE_X22Y20.F1      net (fanout=4)        1.007   gary_cpu_data_in<13>
    SLICE_X22Y20.X       Tilo                  0.486   AGNUS1/bl1/height<13>
                                                       GARY1/custom_data_in<13>1
    SLICE_X1Y19.BX       net (fanout=70)       2.398   custom_data_in<13>
    SLICE_X1Y19.CLK      Tckdi       (-Th)     0.283   AGNUS1/bl1/bltafwm<13>
                                                       AGNUS1/bl1/bltafwm_13
    -------------------------------------------------  ---------------------------
    Total                                      8.813ns (2.174ns logic, 6.639ns route)
                                                       (24.7% logic, 75.3% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_13 (SLICE_X1Y21.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.021ns (data path)
  Source:               cpu_data<13> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_13 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.021ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<13> to AGNUS1/bl1/bltalwm_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P139.I               Tiopi                 1.530   cpu_data<13>
                                                       cpu_data<13>
                                                       cpu_data_13_IOBUF/IBUF
    SLICE_X19Y23.F3      net (fanout=21)       3.234   N948
    SLICE_X19Y23.X       Tilo                  0.441   gary_cpu_data_in<13>
                                                       gary_cpu_data_in<13>1
    SLICE_X22Y20.F1      net (fanout=4)        1.007   gary_cpu_data_in<13>
    SLICE_X22Y20.X       Tilo                  0.486   AGNUS1/bl1/height<13>
                                                       GARY1/custom_data_in<13>1
    SLICE_X1Y21.BY       net (fanout=70)       2.560   custom_data_in<13>
    SLICE_X1Y21.CLK      Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<12>
                                                       AGNUS1/bl1/bltalwm_13
    -------------------------------------------------  ---------------------------
    Total                                      9.021ns (2.220ns logic, 6.801ns route)
                                                       (24.6% logic, 75.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_2 (SLICE_X12Y20.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.055ns (data path)
  Source:               cpu_data<2> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.055ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<2> to AGNUS1/bl1/bltalwm_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P156.I               Tiopi                 1.530   cpu_data<2>
                                                       cpu_data<2>
                                                       cpu_data_2_IOBUF/IBUF
    SLICE_X20Y25.F4      net (fanout=20)       4.353   N959
    SLICE_X20Y25.X       Tilo                  0.486   DENISE1/sprm0/sps5/shiftb<13>
                                                       gary_cpu_data_in<2>1
    SLICE_X23Y25.F3      net (fanout=3)        0.608   gary_cpu_data_in<2>
    SLICE_X23Y25.X       Tilo                  0.441   AGNUS1/bl1/bltadat<2>
                                                       GARY1/custom_data_in<2>1
    SLICE_X12Y20.BY      net (fanout=99)       1.874   custom_data_in<2>
    SLICE_X12Y20.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<2>
                                                       AGNUS1/bl1/bltalwm_2
    -------------------------------------------------  ---------------------------
    Total                                      9.055ns (2.220ns logic, 6.835ns route)
                                                       (24.5% logic, 75.5% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_11 (SLICE_X1Y12.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.419ns (data path)
  Source:               cpu_data<11> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_11 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.419ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<11> to AGNUS1/bl1/bltafwm_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P144.I               Tiopi                 1.530   cpu_data<11>
                                                       cpu_data<11>
                                                       cpu_data_11_IOBUF/IBUF
    SLICE_X23Y21.G4      net (fanout=21)       3.173   N950
    SLICE_X23Y21.Y       Tilo                  0.441   DENISE1/sprm0/sps4/datlb<13>
                                                       gary_cpu_data_in<11>1
    SLICE_X22Y18.F1      net (fanout=3)        0.494   gary_cpu_data_in<11>
    SLICE_X22Y18.X       Tilo                  0.486   AGNUS1/bl1/height<11>
                                                       GARY1/custom_data_in<11>1
    SLICE_X1Y12.BY       net (fanout=72)       3.532   custom_data_in<11>
    SLICE_X1Y12.CLK      Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<11>
                                                       AGNUS1/bl1/bltafwm_11
    -------------------------------------------------  ---------------------------
    Total                                      9.419ns (2.220ns logic, 7.199ns route)
                                                       (23.6% logic, 76.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_0 (SLICE_X10Y14.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.482ns (data path)
  Source:               cpu_data<0> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.482ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<0> to AGNUS1/bl1/bltafwm_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P150.I               Tiopi                 1.530   cpu_data<0>
                                                       cpu_data<0>
                                                       cpu_data_0_IOBUF/IBUF
    SLICE_X17Y20.F1      net (fanout=21)       3.981   N961
    SLICE_X17Y20.X       Tilo                  0.441   gary_cpu_data_in<0>
                                                       gary_cpu_data_in<0>1
    SLICE_X17Y13.G4      net (fanout=3)        1.594   gary_cpu_data_in<0>
    SLICE_X17Y13.Y       Tilo                  0.441   AGNUS1/bl1/bltadat<0>
                                                       GARY1/custom_data_in<0>2
    SLICE_X10Y14.BX      net (fanout=92)       1.778   custom_data_in<0>
    SLICE_X10Y14.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltafwm<0>
                                                       AGNUS1/bl1/bltafwm_0
    -------------------------------------------------  ---------------------------
    Total                                      9.482ns (2.129ns logic, 7.353ns route)
                                                       (22.5% logic, 77.5% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_5 (SLICE_X8Y13.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.551ns (data path)
  Source:               cpu_data<5> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_5 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.551ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<5> to AGNUS1/bl1/bltalwm_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P165.I               Tiopi                 1.530   cpu_data<5>
                                                       cpu_data<5>
                                                       cpu_data_5_IOBUF/IBUF
    SLICE_X22Y24.G4      net (fanout=19)       3.905   N956
    SLICE_X22Y24.Y       Tilo                  0.486   _l_data_1
                                                       gary_cpu_data_in<5>1
    SLICE_X17Y16.F1      net (fanout=4)        1.159   gary_cpu_data_in<5>
    SLICE_X17Y16.X       Tilo                  0.441   AGNUS1/bl1/bltadat<5>
                                                       GARY1/custom_data_in<5>1
    SLICE_X8Y13.BY       net (fanout=89)       2.267   custom_data_in<5>
    SLICE_X8Y13.CLK      Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<5>
                                                       AGNUS1/bl1/bltalwm_5
    -------------------------------------------------  ---------------------------
    Total                                      9.551ns (2.220ns logic, 7.331ns route)
                                                       (23.2% logic, 76.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_8 (SLICE_X6Y12.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.689ns (data path)
  Source:               cpu_data<8> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.689ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<8> to AGNUS1/bl1/bltafwm_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P152.I               Tiopi                 1.530   cpu_data<8>
                                                       cpu_data<8>
                                                       cpu_data_8_IOBUF/IBUF
    SLICE_X23Y17.F3      net (fanout=22)       4.705   N953
    SLICE_X23Y17.X       Tilo                  0.441   DENISE1/sprm0/sps2/datlb<14>
                                                       gary_cpu_data_in<8>1
    SLICE_X11Y14.F1      net (fanout=3)        0.843   gary_cpu_data_in<8>
    SLICE_X11Y14.X       Tilo                  0.441   AGNUS1/bl1/bltadat<8>
                                                       GARY1/custom_data_in<8>1
    SLICE_X6Y12.BY       net (fanout=72)       1.966   custom_data_in<8>
    SLICE_X6Y12.CLK      Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<8>
                                                       AGNUS1/bl1/bltafwm_8
    -------------------------------------------------  ---------------------------
    Total                                      9.689ns (2.175ns logic, 7.514ns route)
                                                       (22.4% logic, 77.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_4 (SLICE_X16Y15.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.830ns (data path)
  Source:               cpu_data<4> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.830ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<4> to AGNUS1/bl1/bltafwm_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P166.I               Tiopi                 1.530   cpu_data<4>
                                                       cpu_data<4>
                                                       cpu_data_4_IOBUF/IBUF
    SLICE_X22Y24.F1      net (fanout=19)       4.017   N957
    SLICE_X22Y24.X       Tilo                  0.486   _l_data_1
                                                       gary_cpu_data_in<4>1
    SLICE_X17Y12.G4      net (fanout=6)        0.979   gary_cpu_data_in<4>
    SLICE_X17Y12.Y       Tilo                  0.441   AGNUS1/bl1/bltadat<4>
                                                       GARY1/custom_data_in<4>1
    SLICE_X16Y15.BY      net (fanout=93)       2.614   custom_data_in<4>
    SLICE_X16Y15.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<4>
                                                       AGNUS1/bl1/bltafwm_4
    -------------------------------------------------  ---------------------------
    Total                                      9.830ns (2.220ns logic, 7.610ns route)
                                                       (22.6% logic, 77.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_7 (SLICE_X7Y17.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.871ns (data path)
  Source:               cpu_data<7> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.871ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<7> to AGNUS1/bl1/bltalwm_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P155.I               Tiopi                 1.530   cpu_data<7>
                                                       cpu_data<7>
                                                       cpu_data_7_IOBUF/IBUF
    SLICE_X27Y21.G2      net (fanout=22)       4.501   N954
    SLICE_X27Y21.Y       Tilo                  0.441   MIA1/magic_r_w<12>
                                                       gary_cpu_data_in<7>1
    SLICE_X22Y17.F2      net (fanout=5)        1.704   gary_cpu_data_in<7>
    SLICE_X22Y17.X       Tilo                  0.486   AGNUS1/bl1/bltadat<7>
                                                       GARY1/custom_data_in<7>1
    SLICE_X7Y17.BX       net (fanout=84)       1.492   custom_data_in<7>
    SLICE_X7Y17.CLK      Tckdi       (-Th)     0.283   AGNUS1/bl1/bltalwm<7>
                                                       AGNUS1/bl1/bltalwm_7
    -------------------------------------------------  ---------------------------
    Total                                      9.871ns (2.174ns logic, 7.697ns route)
                                                       (22.0% logic, 78.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_11 (SLICE_X3Y12.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.993ns (data path)
  Source:               cpu_data<11> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_11 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.993ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<11> to AGNUS1/bl1/bltalwm_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P144.I               Tiopi                 1.530   cpu_data<11>
                                                       cpu_data<11>
                                                       cpu_data_11_IOBUF/IBUF
    SLICE_X23Y21.G4      net (fanout=21)       3.173   N950
    SLICE_X23Y21.Y       Tilo                  0.441   DENISE1/sprm0/sps4/datlb<13>
                                                       gary_cpu_data_in<11>1
    SLICE_X22Y18.F1      net (fanout=3)        0.494   gary_cpu_data_in<11>
    SLICE_X22Y18.X       Tilo                  0.486   AGNUS1/bl1/height<11>
                                                       GARY1/custom_data_in<11>1
    SLICE_X3Y12.BY       net (fanout=72)       4.106   custom_data_in<11>
    SLICE_X3Y12.CLK      Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<11>
                                                       AGNUS1/bl1/bltalwm_11
    -------------------------------------------------  ---------------------------
    Total                                      9.993ns (2.220ns logic, 7.773ns route)
                                                       (22.2% logic, 77.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_6 (SLICE_X8Y14.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      10.050ns (data path)
  Source:               cpu_data<6> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      10.050ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<6> to AGNUS1/bl1/bltalwm_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P161.I               Tiopi                 1.530   cpu_data<6>
                                                       cpu_data<6>
                                                       cpu_data_6_IOBUF/IBUF
    SLICE_X27Y24.G4      net (fanout=19)       5.161   N955
    SLICE_X27Y24.Y       Tilo                  0.441   DENISE1/sprm0/sps5/armed
                                                       gary_cpu_data_in<6>1
    SLICE_X19Y15.F1      net (fanout=4)        1.718   gary_cpu_data_in<6>
    SLICE_X19Y15.X       Tilo                  0.441   AGNUS1/bl1/bltadat<6>
                                                       GARY1/custom_data_in<6>1
    SLICE_X8Y14.BY       net (fanout=91)       0.996   custom_data_in<6>
    SLICE_X8Y14.CLK      Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<6>
                                                       AGNUS1/bl1/bltalwm_6
    -------------------------------------------------  ---------------------------
    Total                                     10.050ns (2.175ns logic, 7.875ns route)
                                                       (21.6% logic, 78.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_7 (SLICE_X12Y18.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      10.723ns (data path)
  Source:               cpu_data<7> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      10.723ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<7> to AGNUS1/bl1/bltafwm_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P155.I               Tiopi                 1.530   cpu_data<7>
                                                       cpu_data<7>
                                                       cpu_data_7_IOBUF/IBUF
    SLICE_X27Y21.G2      net (fanout=22)       4.501   N954
    SLICE_X27Y21.Y       Tilo                  0.441   MIA1/magic_r_w<12>
                                                       gary_cpu_data_in<7>1
    SLICE_X22Y17.F2      net (fanout=5)        1.704   gary_cpu_data_in<7>
    SLICE_X22Y17.X       Tilo                  0.486   AGNUS1/bl1/bltadat<7>
                                                       GARY1/custom_data_in<7>1
    SLICE_X12Y18.BY      net (fanout=84)       2.298   custom_data_in<7>
    SLICE_X12Y18.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<7>
                                                       AGNUS1/bl1/bltafwm_7
    -------------------------------------------------  ---------------------------
    Total                                     10.723ns (2.220ns logic, 8.503ns route)
                                                       (20.7% logic, 79.3% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_12 (SLICE_X1Y20.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      10.766ns (data path)
  Source:               cpu_data<12> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_12 (FF)
  Requirement:          0.000ns
  Data Path Delay:      10.766ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<12> to AGNUS1/bl1/bltafwm_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P141.I               Tiopi                 1.530   cpu_data<12>
                                                       cpu_data<12>
                                                       cpu_data_12_IOBUF/IBUF
    SLICE_X22Y25.F1      net (fanout=23)       3.832   N949
    SLICE_X22Y25.X       Tilo                  0.486   cpu_address_out<6>
                                                       gary_cpu_data_in<12>1
    SLICE_X23Y24.F4      net (fanout=4)        0.299   gary_cpu_data_in<12>
    SLICE_X23Y24.X       Tilo                  0.441   AGNUS1/bl1/height<12>
                                                       GARY1/custom_data_in<12>1
    SLICE_X1Y20.BX       net (fanout=70)       4.461   custom_data_in<12>
    SLICE_X1Y20.CLK      Tckdi       (-Th)     0.283   AGNUS1/bl1/bltafwm<12>
                                                       AGNUS1/bl1/bltafwm_12
    -------------------------------------------------  ---------------------------
    Total                                     10.766ns (2.174ns logic, 8.592ns route)
                                                       (20.2% logic, 79.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_12 (SLICE_X1Y21.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      10.766ns (data path)
  Source:               cpu_data<12> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_12 (FF)
  Requirement:          0.000ns
  Data Path Delay:      10.766ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<12> to AGNUS1/bl1/bltalwm_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P141.I               Tiopi                 1.530   cpu_data<12>
                                                       cpu_data<12>
                                                       cpu_data_12_IOBUF/IBUF
    SLICE_X22Y25.F1      net (fanout=23)       3.832   N949
    SLICE_X22Y25.X       Tilo                  0.486   cpu_address_out<6>
                                                       gary_cpu_data_in<12>1
    SLICE_X23Y24.F4      net (fanout=4)        0.299   gary_cpu_data_in<12>
    SLICE_X23Y24.X       Tilo                  0.441   AGNUS1/bl1/height<12>
                                                       GARY1/custom_data_in<12>1
    SLICE_X1Y21.BX       net (fanout=70)       4.461   custom_data_in<12>
    SLICE_X1Y21.CLK      Tckdi       (-Th)     0.283   AGNUS1/bl1/bltalwm<12>
                                                       AGNUS1/bl1/bltalwm_12
    -------------------------------------------------  ---------------------------
    Total                                     10.766ns (2.174ns logic, 8.592ns route)
                                                       (20.2% logic, 79.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_6 (SLICE_X13Y17.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      10.852ns (data path)
  Source:               cpu_data<6> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      10.852ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<6> to AGNUS1/bl1/bltafwm_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P161.I               Tiopi                 1.530   cpu_data<6>
                                                       cpu_data<6>
                                                       cpu_data_6_IOBUF/IBUF
    SLICE_X27Y24.G4      net (fanout=19)       5.161   N955
    SLICE_X27Y24.Y       Tilo                  0.441   DENISE1/sprm0/sps5/armed
                                                       gary_cpu_data_in<6>1
    SLICE_X19Y15.F1      net (fanout=4)        1.718   gary_cpu_data_in<6>
    SLICE_X19Y15.X       Tilo                  0.441   AGNUS1/bl1/bltadat<6>
                                                       GARY1/custom_data_in<6>1
    SLICE_X13Y17.BY      net (fanout=91)       1.798   custom_data_in<6>
    SLICE_X13Y17.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<5>
                                                       AGNUS1/bl1/bltafwm_6
    -------------------------------------------------  ---------------------------
    Total                                     10.852ns (2.175ns logic, 8.677ns route)
                                                       (20.0% logic, 80.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_15 (SLICE_X1Y17.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      12.445ns (data path)
  Source:               cpu_data<15> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_15 (FF)
  Requirement:          0.000ns
  Data Path Delay:      12.445ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<15> to AGNUS1/bl1/bltalwm_15
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P135.I               Tiopi                 1.530   cpu_data<15>
                                                       cpu_data<15>
                                                       cpu_data_15_IOBUF/IBUF
    SLICE_X23Y31.F1      net (fanout=27)       3.996   N946
    SLICE_X23Y31.X       Tilo                  0.441   GAYLE1/empty_wr
                                                       gary_cpu_data_in<15>1
    SLICE_X22Y33.F1      net (fanout=5)        2.735   gary_cpu_data_in<15>
    SLICE_X22Y33.X       Tilo                  0.486   AGNUS1/bpd1/vdiwstop<7>
                                                       GARY1/custom_data_in<15>1
    SLICE_X1Y17.BY       net (fanout=131)      3.494   custom_data_in<15>
    SLICE_X1Y17.CLK      Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<14>
                                                       AGNUS1/bl1/bltalwm_15
    -------------------------------------------------  ---------------------------
    Total                                     12.445ns (2.220ns logic, 10.225ns route)
                                                       (17.8% logic, 82.2% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_15 (SLICE_X1Y20.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      12.716ns (data path)
  Source:               cpu_data<15> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_15 (FF)
  Requirement:          0.000ns
  Data Path Delay:      12.716ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<15> to AGNUS1/bl1/bltafwm_15
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P135.I               Tiopi                 1.530   cpu_data<15>
                                                       cpu_data<15>
                                                       cpu_data_15_IOBUF/IBUF
    SLICE_X23Y31.F1      net (fanout=27)       3.996   N946
    SLICE_X23Y31.X       Tilo                  0.441   GAYLE1/empty_wr
                                                       gary_cpu_data_in<15>1
    SLICE_X22Y33.F1      net (fanout=5)        2.735   gary_cpu_data_in<15>
    SLICE_X22Y33.X       Tilo                  0.486   AGNUS1/bpd1/vdiwstop<7>
                                                       GARY1/custom_data_in<15>1
    SLICE_X1Y20.BY       net (fanout=131)      3.765   custom_data_in<15>
    SLICE_X1Y20.CLK      Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<12>
                                                       AGNUS1/bl1/bltafwm_15
    -------------------------------------------------  ---------------------------
    Total                                     12.716ns (2.220ns logic, 10.496ns route)
                                                       (17.5% logic, 82.5% route)

--------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_chip28
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_chip28                      |     35.242ns|     30.712ns|     32.165ns|            0|            0|      1807016|    154406524|
| TS_chip7                      |    140.968ns|    128.660ns|          N/A|            0|            0|    154406524|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.


Timing summary:
---------------

Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)

Constraints cover 156215758 paths, 0 nets, and 26409 connections

Design statistics:
   Minimum period: 128.660ns{1}   (Maximum frequency:   7.772MHz)
   Maximum path delay from/to any node:  16.458ns


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Thu Sep 17 17:37:44 2026 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 419 MB



