TS11 maximum
21.322ns (requirement - data path)
  Source:               RAM1/_ce_2 (FF)
  Destination:          _ram_ce<2> (PAD)
  Requirement:          33.000ns
  Data Path Delay:      11.678ns (Levels of Logic = 1)
  Source Clock:         clk28m rising at 0.000ns

  Maximum Data Path: RAM1/_ce_2 to _ram_ce<2>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X17Y29.XQ      Tcko                  0.720   _ce_2
                                                       RAM1/_ce_2
    P15.O1               net (fanout=1)        3.952   _ce_2
    P15.PAD              Tioop                 7.006   _ram_ce<2>
                                                       &ram_ce_2_OBUF
                                                       _ram_ce<2>
    -------------------------------------------------  ---------------------------
    Total                                     11.678ns (7.726ns logic, 3.952ns route)
                                                       (66.2% logic, 33.8% route)

TS11 minimum
8.250ns (data path)
  Source:               RAM1/_ble (FF)
  Destination:          _ram_ble (PAD)
  Requirement:          0.000ns
  Data Path Delay:      8.250ns (Levels of Logic = 1)

  Minimum Data Path: RAM1/_ble to _ram_ble
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y15.YQ       Tcko                  0.576   _ble
                                                       RAM1/_ble
    P42.O1               net (fanout=1)        0.960   _ble
    P42.PAD              Tioop                 6.714   _ram_ble
                                                       &ram_ble_OBUF
                                                       _ram_ble
    -------------------------------------------------  ---------------------------
    Total                                      8.250ns (7.290ns logic, 0.960ns route)
                                                       (88.4% logic, 11.6% route)

TS20 maximum
22.244ns (requirement - data path)
  Source:               cpu_data<8> (PAD)
  Destination:          RAM1/write_data_8 (FF)
  Requirement:          33.000ns
  Data Path Delay:      10.756ns (Levels of Logic = 3)
  Destination Clock:    clk28m rising at 0.000ns

  Maximum Data Path: cpu_data<8> to RAM1/write_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P152.I               Tiopi                 1.918   cpu_data<8>
                                                       cpu_data<8>
                                                       cpu_data_8_IOBUF/IBUF
    SLICE_X23Y17.F3      net (fanout=22)       5.881   N953
    SLICE_X23Y17.X       Tilo                  0.551   DENISE1/sprm0/sps2/datlb<14>
                                                       gary_cpu_data_in<8>1
    SLICE_X6Y19.F4       net (fanout=3)        1.716   gary_cpu_data_in<8>
    SLICE_X6Y19.CLK      Tfck                  0.690   write_data_8
                                                       GARY1/ram_data_in<8>
                                                       RAM1/write_data_8
    -------------------------------------------------  ---------------------------
    Total                                     10.756ns (3.159ns logic, 7.597ns route)
                                                       (29.4% logic, 70.6% route)

TS20 minimum
5.974ns (data path)
  Source:               cpu_data<13> (PAD)
  Destination:          RAM1/write_data_13 (FF)
  Requirement:          0.000ns
  Data Path Delay:      5.974ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<13> to RAM1/write_data_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P139.I               Tiopi                 1.530   cpu_data<13>
                                                       cpu_data<13>
                                                       cpu_data_13_IOBUF/IBUF
    SLICE_X19Y23.F3      net (fanout=21)       3.234   N948
    SLICE_X19Y23.X       Tilo                  0.441   gary_cpu_data_in<13>
                                                       gary_cpu_data_in<13>1
    SLICE_X9Y23.F3       net (fanout=4)        0.708   gary_cpu_data_in<13>
    SLICE_X9Y23.CLK      Tckf        (-Th)    -0.061   write_data_13
                                                       GARY1/ram_data_in<13>
                                                       RAM1/write_data_13
    -------------------------------------------------  ---------------------------
    Total                                      5.974ns (2.032ns logic, 3.942ns route)
                                                       (34.0% logic, 66.0% route)

TS21 maximum
3.500ns (requirement - data path)
  Source:               CPU1/cache_data_selected (FF)
  Destination:          cpu_data<3> (PAD)
  Requirement:          16.000ns
  Data Path Delay:      12.500ns (Levels of Logic = 2)
  Source Clock:         cpu_clk_OBUF falling at 8.292ns

  Maximum Data Path: CPU1/cache_data_selected to cpu_data<3>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X47Y40.XQ      Tcko                  0.720   CPU1/cache_data_selected
                                                       CPU1/cache_data_selected
    SLICE_X47Y33.F3      net (fanout=19)       1.743   CPU1/cache_data_selected
    SLICE_X47Y33.X       Tilo                  0.551   cpu_data_3_IOBUF
                                                       CPU1/data_mux0000<3>1
    P162.O1              net (fanout=1)        2.480   cpu_data_3_IOBUF
    P162.PAD             Tioop                 7.006   cpu_data<3>
                                                       cpu_data_3_IOBUF/OBUFT
                                                       cpu_data<3>
    -------------------------------------------------  ---------------------------
    Total                                     12.500ns (8.277ns logic, 4.223ns route)
                                                       (66.2% logic, 33.8% route)

TS21 minimum
9.289ns (data path)
  Source:               CPU1/cache_data_selected (FF)
  Destination:          cpu_data<0> (PAD)
  Requirement:          0.000ns
  Data Path Delay:      9.289ns (Levels of Logic = 2)

  Minimum Data Path: CPU1/cache_data_selected to cpu_data<0>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X47Y40.XQ      Tcko                  0.576   CPU1/cache_data_selected
                                                       CPU1/cache_data_selected
    SLICE_X46Y40.F4      net (fanout=19)       0.431   CPU1/cache_data_selected
    SLICE_X46Y40.X       Tilo                  0.486   PAULA1/ad1/vol0<1>
                                                       CPU1/data_mux0000<0>1
    P150.O1              net (fanout=1)        1.082   cpu_data_0_IOBUF
    P150.PAD             Tioop                 6.714   cpu_data<0>
                                                       cpu_data_0_IOBUF/OBUFT
                                                       cpu_data<0>
    -------------------------------------------------  ---------------------------
    Total                                      9.289ns (7.776ns logic, 1.513ns route)
                                                       (83.7% logic, 16.3% route)

TS22 maximum
0.290ns (requirement - data path)
  Source:               CPU1/read_ack (FF)
  Destination:          _cpu_dtack (PAD)
  Requirement:          5.750ns
  Data Path Delay:      5.460ns (Levels of Logic = 3)
  Source Clock:         cpu_clk_OBUF rising at 0.000ns

  Maximum Data Path: CPU1/read_ack to _cpu_dtack
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X49Y42.YQ      Tcko                  0.720   CPU1/read_ack
                                                       CPU1/read_ack
    SLICE_X48Y43.F4      net (fanout=1)        0.372   CPU1/read_ack
    SLICE_X48Y43.X       Tilo                  0.608   PAULA1/ad1/dac0/leftdac/pwmcounter<2>
                                                       CPU1/cpu_read_wait1
    SLICE_X46Y43.G2      net (fanout=1)        0.610   CPU1/cpu_read_wait
    SLICE_X46Y43.Y       Tilo                  0.608   AMBER1/lbfo2<12>
                                                       CPU1/_dtack1
    P138.O1              net (fanout=1)        0.900   &cpu_dtack_OBUF
    P138.PAD             Tioop                 1.642   _cpu_dtack
                                                       &cpu_dtack_OBUF
                                                       _cpu_dtack
    -------------------------------------------------  ---------------------------
    Total                                      5.460ns (3.578ns logic, 1.882ns route)
                                                       (65.5% logic, 34.5% route)

TS22 minimum
3.694ns (data path)
  Source:               CPU1/cache_data_selected (FF)
  Destination:          _cpu_dtack (PAD)
  Requirement:          0.000ns
  Data Path Delay:      3.694ns (Levels of Logic = 2)

  Minimum Data Path: CPU1/cache_data_selected to _cpu_dtack
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X47Y40.XQ      Tcko                  0.576   CPU1/cache_data_selected
                                                       CPU1/cache_data_selected
    SLICE_X46Y43.G1      net (fanout=19)       0.562   CPU1/cache_data_selected
    SLICE_X46Y43.Y       Tilo                  0.486   AMBER1/lbfo2<12>
                                                       CPU1/_dtack1
    P138.O1              net (fanout=1)        0.720   &cpu_dtack_OBUF
    P138.PAD             Tioop                 1.350   _cpu_dtack
                                                       &cpu_dtack_OBUF
                                                       _cpu_dtack
    -------------------------------------------------  ---------------------------
    Total                                      3.694ns (2.412ns logic, 1.282ns route)
                                                       (65.3% logic, 34.7% route)

TS23 maximum
11.045ns (requirement - data path)
  Source:               _cpu_lds (PAD)
  Destination:          CPU1/cache_data_selected (FF)
  Requirement:          20.000ns
  Data Path Delay:      8.955ns (Levels of Logic = 3)
  Destination Clock:    cpu_clk_OBUF falling at 8.292ns

  Maximum Data Path: _cpu_lds to CPU1/cache_data_selected
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P143.I               Tiopi                 1.918   _cpu_lds
                                                       _cpu_lds
                                                       &cpu_lds_IBUF
    SLICE_X53Y29.F3      net (fanout=5)        2.937   &cpu_lds_IBUF
    SLICE_X53Y29.X       Tif5x                 0.911   PAULA1/ad1/dac0/ldatatmp<12>
                                                       CPU1/cache_data_selected_mux000043_SW01
                                                       CPU1/cache_data_selected_mux000043_SW0_f5
    SLICE_X47Y40.BX      net (fanout=1)        2.486   CPU1/N1226
    SLICE_X47Y40.CLK     Tdick                 0.703   CPU1/cache_data_selected
                                                       CPU1/cache_data_selected_mux000053_f5
                                                       CPU1/cache_data_selected
    -------------------------------------------------  ---------------------------
    Total                                      8.955ns (3.532ns logic, 5.423ns route)
                                                       (39.4% logic, 60.6% route)

TS23 minimum
4.562ns (data path)
  Source:               _cpu_uds (PAD)
  Destination:          CPU1/cache_lookup_hit (FF)
  Requirement:          0.000ns
  Data Path Delay:      4.562ns (Levels of Logic = 3)

  Minimum Data Path: _cpu_uds to CPU1/cache_lookup_hit
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P146.I               Tiopi                 1.530   _cpu_uds
                                                       _cpu_uds
                                                       &cpu_uds_IBUF
    SLICE_X52Y24.F4      net (fanout=5)        1.358   &cpu_uds_IBUF
    SLICE_X52Y24.X       Tilo                  0.486   PAULA1/dmacon<0>
                                                       CPU1/cache_lookup_hit_and0000_SW0
    SLICE_X48Y32.G4      net (fanout=1)        1.082   CPU1/N161
    SLICE_X48Y32.CLK     Tckg        (-Th)    -0.106   CPU1/cache_lookup_hit
                                                       CPU1/cache_lookup_hit_and0000
                                                       CPU1/cache_lookup_hit
    -------------------------------------------------  ---------------------------
    Total                                      4.562ns (2.122ns logic, 2.440ns route)
                                                       (46.5% logic, 53.5% route)

TS24 maximum
2.540ns (requirement - data path)
  Source:               CPU1/read_data_held_1 (FF)
  Destination:          cpu_data<1> (PAD)
  Requirement:          16.000ns
  Data Path Delay:      13.460ns (Levels of Logic = 2)
  Source Clock:         clk rising at 0.000ns

  Maximum Data Path: CPU1/read_data_held_1 to cpu_data<1>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X33Y43.XQ      Tcko                  0.720   CPU1/read_data_held<1>
                                                       CPU1/read_data_held_1
    SLICE_X49Y41.F1      net (fanout=2)        2.470   CPU1/read_data_held<1>
    SLICE_X49Y41.X       Tilo                  0.551   PAULA1/ad1/ach0/auddat<4>
                                                       CPU1/data_mux0000<1>1
    P154.O1              net (fanout=1)        2.713   cpu_data_1_IOBUF
    P154.PAD             Tioop                 7.006   cpu_data<1>
                                                       cpu_data_1_IOBUF/OBUFT
                                                       cpu_data<1>
    -------------------------------------------------  ---------------------------
    Total                                     13.460ns (8.277ns logic, 5.183ns route)
                                                       (61.5% logic, 38.5% route)

TS24 minimum
10.274ns (data path)
  Source:               CPU1/read_data_held_12 (FF)
  Destination:          cpu_data<12> (PAD)
  Requirement:          0.000ns
  Data Path Delay:      10.274ns (Levels of Logic = 2)

  Minimum Data Path: CPU1/read_data_held_12 to cpu_data<12>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y34.XQ      Tcko                  0.576   CPU1/read_data_held<12>
                                                       CPU1/read_data_held_12
    SLICE_X53Y34.F2      net (fanout=2)        1.604   CPU1/read_data_held<12>
    SLICE_X53Y34.X       Tilo                  0.441   AMBER1/lbfo2<6>
                                                       CPU1/data_mux0000<12>1
    P141.O1              net (fanout=1)        0.939   cpu_data_12_IOBUF
    P141.PAD             Tioop                 6.714   cpu_data<12>
                                                       cpu_data_12_IOBUF/OBUFT
                                                       cpu_data<12>
    -------------------------------------------------  ---------------------------
    Total                                     10.274ns (7.731ns logic, 2.543ns route)
                                                       (75.2% logic, 24.8% route)

TS25 maximum
8.995ns (requirement - (data path - clock path skew + uncertainty))
  Source:               CPU1/read_data_held_5 (FF)
  Destination:          CPU1/Mram_cache_data_lo.A (RAM)
  Requirement:          16.000ns
  Data Path Delay:      7.005ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising
  Destination Clock:    cpu_clk_OBUF falling
  Clock Uncertainty:    0.000ns

  Maximum Data Path: CPU1/read_data_held_5 to CPU1/Mram_cache_data_lo.A
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X30Y41.XQ      Tcko                  0.720   CPU1/read_data_held<5>
                                                       CPU1/read_data_held_5
    SLICE_X44Y25.F4      net (fanout=2)        3.509   CPU1/read_data_held<5>
    SLICE_X44Y25.X       Tilo                  0.608   PAULA1/ad1/ach0/audlen<6>
                                                       CPU1/cache_input_lo<5>1
    RAMB16_X1Y1.DIA5     net (fanout=1)        1.684   CPU1/cache_input_lo<5>
    RAMB16_X1Y1.CLKA     Tbdck                 0.484   CPU1/Mram_cache_data_lo
                                                       CPU1/Mram_cache_data_lo.A
    -------------------------------------------------  ---------------------------
    Total                                      7.005ns (1.812ns logic, 5.193ns route)
                                                       (25.9% logic, 74.1% route)

TS25 minimum
3.554ns (requirement - (clock path skew + uncertainty - data path))
  Source:               CPU1/read_data_held_9 (FF)
  Destination:          CPU1/Mram_cache_data_hi.A (RAM)
  Requirement:          0.000ns
  Data Path Delay:      3.554ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising
  Destination Clock:    cpu_clk_OBUF falling
  Clock Uncertainty:    0.000ns

  Minimum Data Path: CPU1/read_data_held_9 to CPU1/Mram_cache_data_hi.A
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X32Y36.XQ      Tcko                  0.576   CPU1/read_data_held<9>
                                                       CPU1/read_data_held_9
    SLICE_X45Y28.G2      net (fanout=2)        1.450   CPU1/read_data_held<9>
    SLICE_X45Y28.Y       Tilo                  0.441   CPU1/invalidate_sync<1>
                                                       CPU1/cache_input_hi<1>1
    RAMB16_X1Y2.DIA1     net (fanout=1)        1.087   CPU1/cache_input_hi<1>
    RAMB16_X1Y2.CLKA     Tbckd       (-Th)     0.000   CPU1/Mram_cache_data_hi
                                                       CPU1/Mram_cache_data_hi.A
    -------------------------------------------------  ---------------------------
    Total                                      3.554ns (1.017ns logic, 2.537ns route)
                                                       (28.6% logic, 71.4% route)

TS_AUDIT_SRAM_DOE_HOLD maximum
21.135ns (requirement - data path)
  Source:               RAM1/doe_hold (FF)
  Destination:          ram_data<0> (PAD)
  Requirement:          33.000ns
  Data Path Delay:      11.865ns (Levels of Logic = 2)
  Source Clock:         clk28m falling at 17.621ns

  Maximum Data Path: RAM1/doe_hold to ram_data<0>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X5Y15.YQ       Tcko                  0.720   RAM1/doe_hold
                                                       RAM1/doe_hold
    SLICE_X5Y14.F4       net (fanout=1)        0.372   RAM1/doe_hold
    SLICE_X5Y14.X        Tilo                  0.551   AGNUS1/bl1/sign
                                                       RAM1/data_or0000_inv1
    P29.T1               net (fanout=16)       2.974   data_or0000_inv
    P29.PAD              Tiotp                 7.248   ram_data<0>
                                                       ram_data_0_IOBUF/OBUFT
                                                       ram_data<0>
    -------------------------------------------------  ---------------------------
    Total                                     11.865ns (8.519ns logic, 3.346ns route)
                                                       (71.8% logic, 28.2% route)

TS_AUDIT_SRAM_DOE_HOLD minimum
9.262ns (data path)
  Source:               RAM1/doe_hold (FF)
  Destination:          ram_data<11> (PAD)
  Requirement:          0.000ns
  Data Path Delay:      9.262ns (Levels of Logic = 2)

  Minimum Data Path: RAM1/doe_hold to ram_data<11>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X5Y15.YQ       Tcko                  0.576   RAM1/doe_hold
                                                       RAM1/doe_hold
    SLICE_X5Y14.F4       net (fanout=1)        0.297   RAM1/doe_hold
    SLICE_X5Y14.X        Tilo                  0.441   AGNUS1/bl1/sign
                                                       RAM1/data_or0000_inv1
    P48.T1               net (fanout=16)       1.040   data_or0000_inv
    P48.PAD              Tiotp                 6.908   ram_data<11>
                                                       ram_data_11_IOBUF/OBUFT
                                                       ram_data<11>
    -------------------------------------------------  ---------------------------
    Total                                      9.262ns (7.925ns logic, 1.337ns route)
                                                       (85.6% logic, 14.4% route)

TS_AUDIT_SRAM_WRITE_DATA maximum
22.219ns (requirement - data path)
  Source:               RAM1/write_data_15 (FF)
  Destination:          ram_data<15> (PAD)
  Requirement:          33.000ns
  Data Path Delay:      10.781ns (Levels of Logic = 1)
  Source Clock:         clk28m rising at 0.000ns

  Maximum Data Path: RAM1/write_data_15 to ram_data<15>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X8Y30.XQ       Tcko                  0.720   write_data_15
                                                       RAM1/write_data_15
    P43.O1               net (fanout=1)        3.055   write_data_15
    P43.PAD              Tioop                 7.006   ram_data<15>
                                                       ram_data_15_IOBUF/OBUFT
                                                       ram_data<15>
    -------------------------------------------------  ---------------------------
    Total                                     10.781ns (7.726ns logic, 3.055ns route)
                                                       (71.7% logic, 28.3% route)

TS_AUDIT_SRAM_WRITE_DATA minimum
8.276ns (data path)
  Source:               RAM1/write_data_0 (FF)
  Destination:          ram_data<0> (PAD)
  Requirement:          0.000ns
  Data Path Delay:      8.276ns (Levels of Logic = 1)

  Minimum Data Path: RAM1/write_data_0 to ram_data<0>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X8Y27.XQ       Tcko                  0.576   write_data_0
                                                       RAM1/write_data_0
    P29.O1               net (fanout=1)        0.986   write_data_0
    P29.PAD              Tioop                 6.714   ram_data<0>
                                                       ram_data_0_IOBUF/OBUFT
                                                       ram_data<0>
    -------------------------------------------------  ---------------------------
    Total                                      8.276ns (7.290ns logic, 0.986ns route)
                                                       (88.1% logic, 11.9% route)

TS_AUDIT_SRAM_RAM_CAPTURE maximum
15.089ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/aud1/Mram_audpt20 (RAM)
  Destination:          RAM1/write_data_7 (FF)
  Requirement:          35.242ns
  Data Path Delay:      19.779ns (Levels of Logic = 8)
  Clock Path Skew:      -0.020ns (1.842 - 1.862)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk28m rising at 35.242ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/aud1/Mram_audpt20 to RAM1/write_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X32Y13.X       Tshcko                1.784   AGNUS1/address_aud<20>
                                                       AGNUS1/aud1/Mram_audpt20.WE
                                                       AGNUS1/aud1/Mram_audpt20
    SLICE_X27Y13.F2      net (fanout=2)        1.856   AGNUS1/address_aud<20>
    SLICE_X27Y13.X       Tilo                  0.551   AGNUS1/bpd1/ddfseq<0>
                                                       AGNUS1/address_out<20>4
    SLICE_X18Y14.F1      net (fanout=1)        2.265   AGNUS1/address_out<20>4
    SLICE_X18Y14.X       Tilo                  0.608   AGNUS1/cp1/cop1lch<16>
                                                       AGNUS1/address_out<20>54
    SLICE_X22Y29.G1      net (fanout=5)        1.385   dma_address_out<20>
    SLICE_X22Y29.Y       Tilo                  0.608   sel_chip<1>
                                                       GARY1/sel_slow_0_mux000016
    SLICE_X22Y29.F3      net (fanout=1)        0.015   GARY1/sel_slow_0_mux000016/O
    SLICE_X22Y29.X       Tilo                  0.608   sel_chip<1>
                                                       GARY1/sel_chip_1_mux00001
    SLICE_X20Y27.G1      net (fanout=4)        0.578   sel_chip<1>
    SLICE_X20Y27.Y       Tilo                  0.608   AGNUS1/ir2_1
                                                       BMAP1/Mmux_bank233
    SLICE_X20Y27.F2      net (fanout=2)        0.528   Mmux_bank233
    SLICE_X20Y27.X       Tilo                  0.608   AGNUS1/ir2_1
                                                       BMAP1/Mmux_bank243
    SLICE_X21Y23.G1      net (fanout=1)        0.989   bank<0>
    SLICE_X21Y23.Y       Tilo                  0.551   AGNUS1/cp1/copjmp1
                                                       RAM1/enable81
    SLICE_X14Y20.F3      net (fanout=25)       2.784   enable_0
    SLICE_X14Y20.X       Tilo                  0.608   RAM1/write_data_and0000
                                                       RAM1/write_data_and00001
    SLICE_X19Y20.CE      net (fanout=16)       2.243   RAM1/write_data_and0000
    SLICE_X19Y20.CLK     Tceck                 0.602   write_data_7
                                                       RAM1/write_data_7
    -------------------------------------------------  ---------------------------
    Total                                     19.779ns (7.136ns logic, 12.643ns route)
                                                       (36.1% logic, 63.9% route)

TS_AUDIT_SRAM_RAM_CAPTURE minimum
3.282ns (requirement - (clock path skew + uncertainty - data path))
  Source:               PAULA1/pf1/db1/Mram_mem1.B (RAM)
  Destination:          RAM1/write_data_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.635ns (Levels of Logic = 2)
  Clock Path Skew:      -0.001ns (1.842 - 1.843)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk28m rising at 0.000ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: PAULA1/pf1/db1/Mram_mem1.B to RAM1/write_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB16_X0Y4.DOB2     Tbcko                 1.915   PAULA1/pf1/db1/Mram_mem1
                                                       PAULA1/pf1/db1/Mram_mem1.B
    SLICE_X8Y29.G2       net (fanout=3)        1.116   disk_dma_data<2>
    SLICE_X8Y29.Y        Tilo                  0.486   write_data_2
                                                       GARY1/ram_data_in<2>_SW0
    SLICE_X8Y29.F3       net (fanout=1)        0.012   GARY1/ram_data_in<2>_SW0/O
    SLICE_X8Y29.CLK      Tckf        (-Th)    -0.106   write_data_2
                                                       GARY1/ram_data_in<2>
                                                       RAM1/write_data_2
    -------------------------------------------------  ---------------------------
    Total                                      3.635ns (2.507ns logic, 1.128ns route)
                                                       (69.0% logic, 31.0% route)

TS_AUDIT_CPU_ADDRESS_CACHE_READ maximum
993.850ns (requirement - data path)
  Source:               cpu_address<8> (PAD)
  Destination:          CPU1/Mram_cache_data_hi.B (RAM)
  Requirement:          1000.000ns
  Data Path Delay:      6.150ns (Levels of Logic = 1)
  Destination Clock:    cpu_clk_OBUF falling at 8.292ns

  Maximum Data Path: cpu_address<8> to CPU1/Mram_cache_data_hi.B
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P106.I               Tiopi                 1.918   cpu_address<8>
                                                       cpu_address<8>
                                                       cpu_address_8_IBUF
    RAMB16_X1Y2.ADDRB10  net (fanout=5)        3.882   address<8>
    RAMB16_X1Y2.CLKB     Tback                 0.350   CPU1/Mram_cache_data_hi
                                                       CPU1/Mram_cache_data_hi.B
    -------------------------------------------------  ---------------------------
    Total                                      6.150ns (2.268ns logic, 3.882ns route)
                                                       (36.9% logic, 63.1% route)

TS_AUDIT_CPU_ADDRESS_CACHE_READ minimum
3.350ns (data path)
  Source:               cpu_address<11> (PAD)
  Destination:          CPU1/Mram_cache_data_lo.B (RAM)
  Requirement:          0.000ns
  Data Path Delay:      3.350ns (Levels of Logic = 1)

  Minimum Data Path: cpu_address<11> to CPU1/Mram_cache_data_lo.B
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P111.I               Tiopi                 1.530   cpu_address<11>
                                                       cpu_address<11>
                                                       cpu_address_11_IBUF
    RAMB16_X1Y1.ADDRB13  net (fanout=5)        1.820   address<11>
    RAMB16_X1Y1.CLKB     Tbcka       (-Th)     0.000   CPU1/Mram_cache_data_lo
                                                       CPU1/Mram_cache_data_lo.B
    -------------------------------------------------  ---------------------------
    Total                                      3.350ns (1.530ns logic, 1.820ns route)
                                                       (45.7% logic, 54.3% route)

TS_AUDIT_CPU_SRAM_READ_RETURN maximum
19.821ns (requirement - data path)
  Source:               ram_data<1> (PAD)
  Destination:          CPU1/read_data_held_1 (FF)
  Requirement:          33.000ns
  Data Path Delay:      13.179ns (Levels of Logic = 7)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: ram_data<1> to CPU1/read_data_held_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P31.I                Tiopi                 1.918   ram_data<1>
                                                       ram_data<1>
                                                       ram_data_1_IOBUF/IBUF
    SLICE_X14Y27.G4      net (fanout=1)        1.718   N944
    SLICE_X14Y27.Y       Tilo                  0.608   DENISE1/sprm0/sps5/datlb<5>
                                                       RAM1/data_out<1>1
    SLICE_X14Y27.F4      net (fanout=5)        0.374   ram_data_out<1>
    SLICE_X14Y27.X       Tilo                  0.608   DENISE1/sprm0/sps5/datlb<5>
                                                       cpu_data_in<1>259_SW1_SW0
    SLICE_X20Y38.F1      net (fanout=1)        2.719   N1932
    SLICE_X20Y38.X       Tilo                  0.608   PAULA1/dmacon<4>
                                                       cpu_data_in<1>259_SW1
    SLICE_X27Y38.F1      net (fanout=1)        1.260   N1908
    SLICE_X27Y38.X       Tilo                  0.551   DENISE1/bplm0/bpl5dat<13>
                                                       cpu_data_in<1>289_SW0
    SLICE_X33Y43.G3      net (fanout=1)        1.616   N1926
    SLICE_X33Y43.Y       Tilo                  0.551   CPU1/read_data_held<1>
                                                       cpu_data_in<1>311
    SLICE_X33Y43.F4      net (fanout=1)        0.015   cpu_data_in<1>311/O
    SLICE_X33Y43.CLK     Tfck                  0.633   CPU1/read_data_held<1>
                                                       cpu_data_in<1>335
                                                       CPU1/read_data_held_1
    -------------------------------------------------  ---------------------------
    Total                                     13.179ns (5.477ns logic, 7.702ns route)
                                                       (41.6% logic, 58.4% route)

TS_AUDIT_CPU_SRAM_READ_RETURN minimum
5.738ns (data path)
  Source:               ram_data<4> (PAD)
  Destination:          CPU1/read_data_held_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      5.738ns (Levels of Logic = 5)

  Minimum Data Path: ram_data<4> to CPU1/read_data_held_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P65.I                Tiopi                 1.530   ram_data<4>
                                                       ram_data<4>
                                                       ram_data_4_IOBUF/IBUF
    SLICE_X19Y21.G3      net (fanout=1)        1.323   N941
    SLICE_X19Y21.Y       Tilo                  0.441   _l_data_14
                                                       RAM1/data_out<4>1
    SLICE_X19Y21.F4      net (fanout=6)        0.040   ram_data_out<4>
    SLICE_X19Y21.X       Tilo                  0.441   _l_data_14
                                                       cpu_data_in<4>225_SW0
    SLICE_X27Y34.G2      net (fanout=1)        1.449   N1852
    SLICE_X27Y34.Y       Tilo                  0.441   CPU1/read_data_held<4>
                                                       cpu_data_in<4>262_SW0
    SLICE_X27Y34.F3      net (fanout=1)        0.012   cpu_data_in<4>262_SW0/O
    SLICE_X27Y34.CLK     Tckf        (-Th)    -0.061   CPU1/read_data_held<4>
                                                       cpu_data_in<4>262
                                                       CPU1/read_data_held_4
    -------------------------------------------------  ---------------------------
    Total                                      5.738ns (2.914ns logic, 2.824ns route)
                                                       (50.8% logic, 49.2% route)
