TS_R7_CAPTURE_PERIOD setup
Slack (setup path):     3.077ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          CPU1/read_data_held_7 (FF)
  Requirement:          35.243ns
  Data Path Delay:      31.812ns (Levels of Logic = 17)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to CPU1/read_data_held_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y41.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.G2      net (fanout=1)        1.786   AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.Y       Tilo                  0.608   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X20Y31.F3      net (fanout=6)        0.024   AGNUS1/N1_0
    SLICE_X20Y31.X       Tilo                  0.608   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X20Y26.F4      net (fanout=30)       0.384   dma_spr
    SLICE_X20Y26.X       Tilo                  0.608   _l_data_2
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X22Y26.G2      net (fanout=29)       0.606   AGNUS1/N58
    SLICE_X22Y26.Y       Tilo                  0.608   DENISE1/sprm0/sps5/datla<13>
                                                       AGNUS1/dbr_and000073
    SLICE_X22Y26.F4      net (fanout=8)        0.040   AGNUS1/dbr_and0000
    SLICE_X22Y26.X       Tilo                  0.608   DENISE1/sprm0/sps5/datla<13>
                                                       AGNUS1/dbr
    SLICE_X30Y39.F4      net (fanout=38)       1.970   dbr
    SLICE_X30Y39.X       Tilo                  0.608   CPU1/enable114
                                                       CPU1/enable114
    SLICE_X30Y38.G2      net (fanout=2)        0.271   CPU1/enable114
    SLICE_X30Y38.Y       Tilo                  0.608   DENISE1/bplm0/bpl3dat<15>
                                                       CPU1/enable
    SLICE_X29Y36.G4      net (fanout=7)        0.387   enable
    SLICE_X29Y36.Y       Tilo                  0.551   DENISE1/bplm0/bpl6dat<13>
                                                       CPU1/rd1
    SLICE_X28Y31.G3      net (fanout=48)       1.926   cpu_rd
    SLICE_X28Y31.Y       Tilo                  0.608   AGNUS1/N31
                                                       AGNUS1/reg_address<1>1197
    SLICE_X28Y31.F1      net (fanout=1)        0.587   AGNUS1/reg_address<1>1197/O
    SLICE_X28Y31.X       Tilo                  0.608   AGNUS1/N31
                                                       AGNUS1/reg_address<1>11118
    SLICE_X29Y28.G3      net (fanout=9)        0.463   AGNUS1/N31
    SLICE_X29Y28.Y       Tilo                  0.551   PAULA1/N2
                                                       AGNUS1/reg_address<6>74
    SLICE_X32Y39.G2      net (fanout=32)       2.676   reg_address<6>
    SLICE_X32Y39.Y       Tilo                  0.608   USERIO1/osd1/t_ide_config<2>
                                                       PAULA1/pu1/data_out<13>11_SW0
    SLICE_X27Y47.G4      net (fanout=2)        2.722   PAULA1/pu1/N848
    SLICE_X27Y47.Y       Tilo                  0.551   PAULA1/pu1/rxshift<10>
                                                       PAULA1/pu1/data_out<13>11
    SLICE_X27Y47.F2      net (fanout=3)        0.578   PAULA1/pu1/N9
    SLICE_X27Y47.X       Tilo                  0.551   PAULA1/pu1/rxshift<10>
                                                       PAULA1/pu1/data_out<13>12
    SLICE_X19Y38.F2      net (fanout=14)       4.133   N2_0
    SLICE_X19Y38.X       Tilo                  0.551   DENISE1/bplm0/bplshft6/shifter<4>
                                                       cpu_data_in<7>269
    SLICE_X23Y36.F4      net (fanout=1)        1.021   cpu_data_in<7>269
    SLICE_X23Y36.X       Tilo                  0.551   cpu_data_in<7>284
                                                       cpu_data_in<7>284
    SLICE_X31Y30.F2      net (fanout=1)        1.499   cpu_data_in<7>284
    SLICE_X31Y30.CLK     Tfck                  0.633   CPU1/read_data_held<7>
                                                       cpu_data_in<7>320
                                                       CPU1/read_data_held_7
    -------------------------------------------------  ---------------------------
    Total                                     31.812ns (10.739ns logic, 21.073ns route)
                                                       (33.8% logic, 66.2% route)

--------------------------------------------------------------------------------


TS_R7_CAPTURE_PERIOD hold
Slack (hold path):      1.593ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/dmacon_7 (FF)
  Destination:          CPU1/read_data_held_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.948ns (Levels of Logic = 2)
  Clock Path Skew:      0.001ns (0.437 - 0.436)
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/dmacon_7 to CPU1/read_data_held_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y28.YQ      Tcko                  0.576   dmacon_7
                                                       AGNUS1/dmacon_7
    SLICE_X31Y30.G1      net (fanout=3)        0.858   dmacon_7
    SLICE_X31Y30.Y       Tilo                  0.441   CPU1/read_data_held<7>
                                                       cpu_data_in<7>230
    SLICE_X31Y30.F3      net (fanout=1)        0.012   cpu_data_in<7>230/O
    SLICE_X31Y30.CLK     Tckf        (-Th)    -0.061   CPU1/read_data_held<7>
                                                       cpu_data_in<7>320
                                                       CPU1/read_data_held_7
    -------------------------------------------------  ---------------------------
    Total                                      1.948ns (1.078ns logic, 0.870ns route)
                                                       (55.3% logic, 44.7% route)

--------------------------------------------------------------------------------


TS_R7_SERVICE_PERIOD setup
Slack (setup path):     21.511ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          CPU1/read_complete (FF)
  Requirement:          35.243ns
  Data Path Delay:      13.378ns (Levels of Logic = 8)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to CPU1/read_complete
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y41.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.G2      net (fanout=1)        1.786   AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.Y       Tilo                  0.608   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X20Y31.F3      net (fanout=6)        0.024   AGNUS1/N1_0
    SLICE_X20Y31.X       Tilo                  0.608   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X20Y26.F4      net (fanout=30)       0.384   dma_spr
    SLICE_X20Y26.X       Tilo                  0.608   _l_data_2
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X22Y26.G2      net (fanout=29)       0.606   AGNUS1/N58
    SLICE_X22Y26.Y       Tilo                  0.608   DENISE1/sprm0/sps5/datla<13>
                                                       AGNUS1/dbr_and000073
    SLICE_X22Y26.F4      net (fanout=8)        0.040   AGNUS1/dbr_and0000
    SLICE_X22Y26.X       Tilo                  0.608   DENISE1/sprm0/sps5/datla<13>
                                                       AGNUS1/dbr
    SLICE_X30Y39.F4      net (fanout=38)       1.970   dbr
    SLICE_X30Y39.X       Tilo                  0.608   CPU1/enable114
                                                       CPU1/enable114
    SLICE_X30Y38.G2      net (fanout=2)        0.271   CPU1/enable114
    SLICE_X30Y38.Y       Tilo                  0.608   DENISE1/bplm0/bpl3dat<15>
                                                       CPU1/enable
    SLICE_X29Y36.G4      net (fanout=7)        0.387   enable
    SLICE_X29Y36.Y       Tilo                  0.551   DENISE1/bplm0/bpl6dat<13>
                                                       CPU1/rd1
    SLICE_X40Y42.CE      net (fanout=48)       1.781   cpu_rd
    SLICE_X40Y42.CLK     Tceck                 0.602   CPU1/read_complete
                                                       CPU1/read_complete
    -------------------------------------------------  ---------------------------
    Total                                     13.378ns (6.129ns logic, 7.249ns route)
                                                       (45.8% logic, 54.2% route)

--------------------------------------------------------------------------------


TS_R7_SERVICE_PERIOD hold
Slack (hold path):      1.395ns (requirement - (clock path skew + uncertainty - data path))
  Source:               CPU1/read_as_seen (FF)
  Destination:          CPU1/read_serviced (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.750ns (Levels of Logic = 0)
  Clock Path Skew:      0.001ns (0.142 - 0.141)
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: CPU1/read_as_seen to CPU1/read_serviced
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y37.YQ      Tcko                  0.576   CPU1/read_as_seen
                                                       CPU1/read_as_seen
    SLICE_X29Y34.SR      net (fanout=4)        1.145   CPU1/read_as_seen
    SLICE_X29Y34.CLK     Tcksr       (-Th)    -0.029   CPU1/read_serviced
                                                       CPU1/read_serviced
    -------------------------------------------------  ---------------------------
    Total                                      1.750ns (0.605ns logic, 1.145ns route)
                                                       (34.6% logic, 65.4% route)

--------------------------------------------------------------------------------


