TS_R4_COMPLETION equivalent PERIOD audit
214490 paths, 13 physical pins across four logical FFs; zero setup/hold errors.
Four destinations partitioned from chip7, with PERIOD TS_chip7 PHASE+0 HIGH50%; all other periods and SYSTEM_JITTER unchanged. Main PCF is unmodified.
Worst paths below are excerpts from completion.twr.

AGNUS1/bl1/busy: all setup
Slack (setup path):     7.184ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          AGNUS1/bl1/busy (FF)
  Requirement:          35.243ns
  Data Path Delay:      27.705ns (Levels of Logic = 14)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to AGNUS1/bl1/busy
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y41.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.G2      net (fanout=1)        1.786   AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.Y       Tilo                  0.608   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X20Y31.F3      net (fanout=6)        0.024   AGNUS1/N1_0
    SLICE_X20Y31.X       Tilo                  0.608   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X20Y26.F4      net (fanout=30)       0.384   dma_spr
    SLICE_X20Y26.X       Tilo                  0.608   _l_data_2
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X22Y26.G2      net (fanout=29)       0.606   AGNUS1/N58
    SLICE_X22Y26.Y       Tilo                  0.608   DENISE1/sprm0/sps5/datla<13>
                                                       AGNUS1/dbr_and000073
    SLICE_X22Y26.F4      net (fanout=8)        0.040   AGNUS1/dbr_and0000
    SLICE_X22Y26.X       Tilo                  0.608   DENISE1/sprm0/sps5/datla<13>
                                                       AGNUS1/dbr
    SLICE_X30Y39.F4      net (fanout=38)       1.970   dbr
    SLICE_X30Y39.X       Tilo                  0.608   CPU1/enable114
                                                       CPU1/enable114
    SLICE_X30Y38.G2      net (fanout=2)        0.271   CPU1/enable114
    SLICE_X30Y38.Y       Tilo                  0.608   DENISE1/bplm0/bpl3dat<15>
                                                       CPU1/enable
    SLICE_X29Y36.G4      net (fanout=7)        0.387   enable
    SLICE_X29Y36.Y       Tilo                  0.551   DENISE1/bplm0/bpl6dat<13>
                                                       CPU1/rd1
    SLICE_X28Y31.G3      net (fanout=48)       1.926   cpu_rd
    SLICE_X28Y31.Y       Tilo                  0.608   AGNUS1/N31
                                                       AGNUS1/reg_address<1>1197
    SLICE_X28Y31.F1      net (fanout=1)        0.587   AGNUS1/reg_address<1>1197/O
    SLICE_X28Y31.X       Tilo                  0.608   AGNUS1/N31
                                                       AGNUS1/reg_address<1>11118
    SLICE_X31Y29.G3      net (fanout=9)        0.824   AGNUS1/N31
    SLICE_X31Y29.Y       Tilo                  0.551   cpu_address_out<3>
                                                       AGNUS1/reg_address<7>63
    SLICE_X16Y15.G2      net (fanout=42)       3.249   reg_address<7>
    SLICE_X16Y15.Y       Tilo                  0.608   AGNUS1/bl1/bltafwm<4>
                                                       AGNUS1/bl1/address_generator_1/bltpth_3_or000021
    SLICE_X16Y15.F3      net (fanout=5)        0.018   AGNUS1/bl1/N5_0
    SLICE_X16Y15.X       Tilo                  0.608   AGNUS1/bl1/bltafwm<4>
                                                       AGNUS1/bl1/bltcon0_7_or000021
    SLICE_X10Y8.F1       net (fanout=10)       2.132   AGNUS1/bl1/N27
    SLICE_X10Y8.X        Tilo                  0.608   DENISE1/sprm0/sps2/datla<7>
                                                       AGNUS1/bl1/busy_or00001
    SLICE_X16Y27.BY      net (fanout=9)        3.214   AGNUS1/bl1/busy_or0000
    SLICE_X16Y27.CLK     Tsrck                 1.169   busy_0
                                                       AGNUS1/bl1/busy
    -------------------------------------------------  ---------------------------
    Total                                     27.705ns (10.287ns logic, 17.418ns route)
                                                       (37.1% logic, 62.9% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/busy: via_done setup
Slack (setup path):     23.045ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          AGNUS1/bl1/busy (FF)
  Requirement:          35.243ns
  Data Path Delay:      11.844ns (Levels of Logic = 6)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to AGNUS1/bl1/busy
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y41.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.G2      net (fanout=1)        1.786   AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.Y       Tilo                  0.608   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X20Y31.F3      net (fanout=6)        0.024   AGNUS1/N1_0
    SLICE_X20Y31.X       Tilo                  0.608   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X20Y26.F4      net (fanout=30)       0.384   dma_spr
    SLICE_X20Y26.X       Tilo                  0.608   _l_data_2
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X22Y26.G2      net (fanout=29)       0.606   AGNUS1/N58
    SLICE_X22Y26.Y       Tilo                  0.608   DENISE1/sprm0/sps5/datla<13>
                                                       AGNUS1/dbr_and000073
    SLICE_X22Y11.G4      net (fanout=8)        1.313   AGNUS1/dbr_and0000
    SLICE_X22Y11.Y       Tilo                  0.608   DENISE1/sprm0/sps6/datla<13>
                                                       AGNUS1/address_out<10>111
    SLICE_X14Y23.G1      net (fanout=24)       2.057   N33_1
    SLICE_X14Y23.Y       Tilo                  0.608   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X16Y27.CE      net (fanout=3)        0.704   int3
    SLICE_X16Y27.CLK     Tceck                 0.602   busy_0
                                                       AGNUS1/bl1/busy
    -------------------------------------------------  ---------------------------
    Total                                     11.844ns (4.970ns logic, 6.874ns route)
                                                       (42.0% logic, 58.0% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/busy: all hold
Slack (hold path):      1.828ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/bl1/blt_state_FSM_FFd4 (FF)
  Destination:          AGNUS1/bl1/busy (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.182ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/bl1/blt_state_FSM_FFd4 to AGNUS1/bl1/busy
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y20.XQ      Tcko                  0.576   AGNUS1/blt_state_FSM_FFd4
                                                       AGNUS1/bl1/blt_state_FSM_FFd4
    SLICE_X14Y23.G2      net (fanout=10)       0.557   AGNUS1/blt_state_FSM_FFd4
    SLICE_X14Y23.Y       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X16Y27.CE      net (fanout=3)        0.563   int3
    SLICE_X16Y27.CLK     Tckce       (-Th)     0.000   busy_0
                                                       AGNUS1/bl1/busy
    -------------------------------------------------  ---------------------------
    Total                                      2.182ns (1.062ns logic, 1.120ns route)
                                                       (48.7% logic, 51.3% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/busy: via_done hold
Slack (hold path):      1.828ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/bl1/blt_state_FSM_FFd4 (FF)
  Destination:          AGNUS1/bl1/busy (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.182ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/bl1/blt_state_FSM_FFd4 to AGNUS1/bl1/busy
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y20.XQ      Tcko                  0.576   AGNUS1/blt_state_FSM_FFd4
                                                       AGNUS1/bl1/blt_state_FSM_FFd4
    SLICE_X14Y23.G2      net (fanout=10)       0.557   AGNUS1/blt_state_FSM_FFd4
    SLICE_X14Y23.Y       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X16Y27.CE      net (fanout=3)        0.563   int3
    SLICE_X16Y27.CLK     Tckce       (-Th)     0.000   busy_0
                                                       AGNUS1/bl1/busy
    -------------------------------------------------  ---------------------------
    Total                                      2.182ns (1.062ns logic, 1.120ns route)
                                                       (48.7% logic, 51.3% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/start: all setup
Slack (setup path):     21.336ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          AGNUS1/bl1/start (FF)
  Requirement:          35.243ns
  Data Path Delay:      13.553ns (Levels of Logic = 7)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to AGNUS1/bl1/start
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y41.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.G2      net (fanout=1)        1.786   AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.Y       Tilo                  0.608   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X20Y31.F3      net (fanout=6)        0.024   AGNUS1/N1_0
    SLICE_X20Y31.X       Tilo                  0.608   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X20Y26.F4      net (fanout=30)       0.384   dma_spr
    SLICE_X20Y26.X       Tilo                  0.608   _l_data_2
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X22Y26.G2      net (fanout=29)       0.606   AGNUS1/N58
    SLICE_X22Y26.Y       Tilo                  0.608   DENISE1/sprm0/sps5/datla<13>
                                                       AGNUS1/dbr_and000073
    SLICE_X22Y11.G4      net (fanout=8)        1.313   AGNUS1/dbr_and0000
    SLICE_X22Y11.Y       Tilo                  0.608   DENISE1/sprm0/sps6/datla<13>
                                                       AGNUS1/address_out<10>111
    SLICE_X14Y23.G1      net (fanout=24)       2.057   N33_1
    SLICE_X14Y23.Y       Tilo                  0.608   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X14Y23.F3      net (fanout=3)        0.021   int3
    SLICE_X14Y23.X       Tilo                  0.608   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X14Y22.SR      net (fanout=2)        1.360   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X14Y22.CLK     Tsrck                 1.026   AGNUS1/bl1/start
                                                       AGNUS1/bl1/start
    -------------------------------------------------  ---------------------------
    Total                                     13.553ns (6.002ns logic, 7.551ns route)
                                                       (44.3% logic, 55.7% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/start: via_done setup
Slack (setup path):     21.336ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          AGNUS1/bl1/start (FF)
  Requirement:          35.243ns
  Data Path Delay:      13.553ns (Levels of Logic = 7)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to AGNUS1/bl1/start
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y41.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.G2      net (fanout=1)        1.786   AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.Y       Tilo                  0.608   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X20Y31.F3      net (fanout=6)        0.024   AGNUS1/N1_0
    SLICE_X20Y31.X       Tilo                  0.608   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X20Y26.F4      net (fanout=30)       0.384   dma_spr
    SLICE_X20Y26.X       Tilo                  0.608   _l_data_2
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X22Y26.G2      net (fanout=29)       0.606   AGNUS1/N58
    SLICE_X22Y26.Y       Tilo                  0.608   DENISE1/sprm0/sps5/datla<13>
                                                       AGNUS1/dbr_and000073
    SLICE_X22Y11.G4      net (fanout=8)        1.313   AGNUS1/dbr_and0000
    SLICE_X22Y11.Y       Tilo                  0.608   DENISE1/sprm0/sps6/datla<13>
                                                       AGNUS1/address_out<10>111
    SLICE_X14Y23.G1      net (fanout=24)       2.057   N33_1
    SLICE_X14Y23.Y       Tilo                  0.608   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X14Y23.F3      net (fanout=3)        0.021   int3
    SLICE_X14Y23.X       Tilo                  0.608   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X14Y22.SR      net (fanout=2)        1.360   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X14Y22.CLK     Tsrck                 1.026   AGNUS1/bl1/start
                                                       AGNUS1/bl1/start
    -------------------------------------------------  ---------------------------
    Total                                     13.553ns (6.002ns logic, 7.551ns route)
                                                       (44.3% logic, 55.7% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/start: all hold
Slack (hold path):      2.885ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/bl1/blt_state_FSM_FFd4 (FF)
  Destination:          AGNUS1/bl1/start (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.239ns (Levels of Logic = 2)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/bl1/blt_state_FSM_FFd4 to AGNUS1/bl1/start
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y20.XQ      Tcko                  0.576   AGNUS1/blt_state_FSM_FFd4
                                                       AGNUS1/bl1/blt_state_FSM_FFd4
    SLICE_X14Y23.G2      net (fanout=10)       0.557   AGNUS1/blt_state_FSM_FFd4
    SLICE_X14Y23.Y       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X14Y23.F3      net (fanout=3)        0.017   int3
    SLICE_X14Y23.X       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X14Y22.SR      net (fanout=2)        1.088   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X14Y22.CLK     Tcksr       (-Th)    -0.029   AGNUS1/bl1/start
                                                       AGNUS1/bl1/start
    -------------------------------------------------  ---------------------------
    Total                                      3.239ns (1.577ns logic, 1.662ns route)
                                                       (48.7% logic, 51.3% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/start: via_done hold
Slack (hold path):      2.885ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/bl1/blt_state_FSM_FFd4 (FF)
  Destination:          AGNUS1/bl1/start (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.239ns (Levels of Logic = 2)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/bl1/blt_state_FSM_FFd4 to AGNUS1/bl1/start
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y20.XQ      Tcko                  0.576   AGNUS1/blt_state_FSM_FFd4
                                                       AGNUS1/bl1/blt_state_FSM_FFd4
    SLICE_X14Y23.G2      net (fanout=10)       0.557   AGNUS1/blt_state_FSM_FFd4
    SLICE_X14Y23.Y       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X14Y23.F3      net (fanout=3)        0.017   int3
    SLICE_X14Y23.X       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X14Y22.SR      net (fanout=2)        1.088   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X14Y22.CLK     Tcksr       (-Th)    -0.029   AGNUS1/bl1/start
                                                       AGNUS1/bl1/start
    -------------------------------------------------  ---------------------------
    Total                                      3.239ns (1.577ns logic, 1.662ns route)
                                                       (48.7% logic, 51.3% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/bltbold_init: all setup
Slack (setup path):     9.134ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          AGNUS1/bl1/bltbold_init (FF)
  Requirement:          35.243ns
  Data Path Delay:      25.755ns (Levels of Logic = 14)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to AGNUS1/bl1/bltbold_init
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y41.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.G2      net (fanout=1)        1.786   AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.Y       Tilo                  0.608   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X20Y31.F3      net (fanout=6)        0.024   AGNUS1/N1_0
    SLICE_X20Y31.X       Tilo                  0.608   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X20Y26.F4      net (fanout=30)       0.384   dma_spr
    SLICE_X20Y26.X       Tilo                  0.608   _l_data_2
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X22Y26.G2      net (fanout=29)       0.606   AGNUS1/N58
    SLICE_X22Y26.Y       Tilo                  0.608   DENISE1/sprm0/sps5/datla<13>
                                                       AGNUS1/dbr_and000073
    SLICE_X22Y26.F4      net (fanout=8)        0.040   AGNUS1/dbr_and0000
    SLICE_X22Y26.X       Tilo                  0.608   DENISE1/sprm0/sps5/datla<13>
                                                       AGNUS1/dbr
    SLICE_X30Y39.F4      net (fanout=38)       1.970   dbr
    SLICE_X30Y39.X       Tilo                  0.608   CPU1/enable114
                                                       CPU1/enable114
    SLICE_X30Y38.G2      net (fanout=2)        0.271   CPU1/enable114
    SLICE_X30Y38.Y       Tilo                  0.608   DENISE1/bplm0/bpl3dat<15>
                                                       CPU1/enable
    SLICE_X29Y36.G4      net (fanout=7)        0.387   enable
    SLICE_X29Y36.Y       Tilo                  0.551   DENISE1/bplm0/bpl6dat<13>
                                                       CPU1/rd1
    SLICE_X28Y31.G3      net (fanout=48)       1.926   cpu_rd
    SLICE_X28Y31.Y       Tilo                  0.608   AGNUS1/N31
                                                       AGNUS1/reg_address<1>1197
    SLICE_X28Y31.F1      net (fanout=1)        0.587   AGNUS1/reg_address<1>1197/O
    SLICE_X28Y31.X       Tilo                  0.608   AGNUS1/N31
                                                       AGNUS1/reg_address<1>11118
    SLICE_X31Y29.G3      net (fanout=9)        0.824   AGNUS1/N31
    SLICE_X31Y29.Y       Tilo                  0.551   cpu_address_out<3>
                                                       AGNUS1/reg_address<7>63
    SLICE_X16Y15.G2      net (fanout=42)       3.249   reg_address<7>
    SLICE_X16Y15.Y       Tilo                  0.608   AGNUS1/bl1/bltafwm<4>
                                                       AGNUS1/bl1/address_generator_1/bltpth_3_or000021
    SLICE_X8Y31.G4       net (fanout=5)        3.198   AGNUS1/bl1/N5_0
    SLICE_X8Y31.Y        Tilo                  0.608   hdd_data_out<10>
                                                       AGNUS1/bl1/bltadat_cmp_eq000012
    SLICE_X8Y31.F3       net (fanout=4)        0.031   AGNUS1/bl1/N24
    SLICE_X8Y31.X        Tilo                  0.608   hdd_data_out<10>
                                                       AGNUS1/bl1/bltbdat_cmp_eq00001
    SLICE_X15Y28.CE      net (fanout=20)       0.752   AGNUS1/bl1/bltbdat_cmp_eq0000
    SLICE_X15Y28.CLK     Tceck                 0.602   AGNUS1/bl1/bltbold_init
                                                       AGNUS1/bl1/bltbold_init
    -------------------------------------------------  ---------------------------
    Total                                     25.755ns (9.720ns logic, 16.035ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/bltbold_init: via_done setup
Slack (setup path):     21.875ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          AGNUS1/bl1/bltbold_init (FF)
  Requirement:          35.243ns
  Data Path Delay:      13.014ns (Levels of Logic = 7)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to AGNUS1/bl1/bltbold_init
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y41.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.G2      net (fanout=1)        1.786   AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.Y       Tilo                  0.608   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X20Y31.F3      net (fanout=6)        0.024   AGNUS1/N1_0
    SLICE_X20Y31.X       Tilo                  0.608   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X20Y26.F4      net (fanout=30)       0.384   dma_spr
    SLICE_X20Y26.X       Tilo                  0.608   _l_data_2
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X22Y26.G2      net (fanout=29)       0.606   AGNUS1/N58
    SLICE_X22Y26.Y       Tilo                  0.608   DENISE1/sprm0/sps5/datla<13>
                                                       AGNUS1/dbr_and000073
    SLICE_X22Y11.G4      net (fanout=8)        1.313   AGNUS1/dbr_and0000
    SLICE_X22Y11.Y       Tilo                  0.608   DENISE1/sprm0/sps6/datla<13>
                                                       AGNUS1/address_out<10>111
    SLICE_X14Y23.G1      net (fanout=24)       2.057   N33_1
    SLICE_X14Y23.Y       Tilo                  0.608   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X14Y23.F3      net (fanout=3)        0.021   int3
    SLICE_X14Y23.X       Tilo                  0.608   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X15Y28.SR      net (fanout=2)        0.821   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X15Y28.CLK     Tsrck                 1.026   AGNUS1/bl1/bltbold_init
                                                       AGNUS1/bl1/bltbold_init
    -------------------------------------------------  ---------------------------
    Total                                     13.014ns (6.002ns logic, 7.012ns route)
                                                       (46.1% logic, 53.9% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/bltbold_init: all hold
Slack (hold path):      2.454ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/bl1/blt_state_FSM_FFd4 (FF)
  Destination:          AGNUS1/bl1/bltbold_init (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.808ns (Levels of Logic = 2)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/bl1/blt_state_FSM_FFd4 to AGNUS1/bl1/bltbold_init
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y20.XQ      Tcko                  0.576   AGNUS1/blt_state_FSM_FFd4
                                                       AGNUS1/bl1/blt_state_FSM_FFd4
    SLICE_X14Y23.G2      net (fanout=10)       0.557   AGNUS1/blt_state_FSM_FFd4
    SLICE_X14Y23.Y       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X14Y23.F3      net (fanout=3)        0.017   int3
    SLICE_X14Y23.X       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X15Y28.SR      net (fanout=2)        0.657   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X15Y28.CLK     Tcksr       (-Th)    -0.029   AGNUS1/bl1/bltbold_init
                                                       AGNUS1/bl1/bltbold_init
    -------------------------------------------------  ---------------------------
    Total                                      2.808ns (1.577ns logic, 1.231ns route)
                                                       (56.2% logic, 43.8% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/bltbold_init: via_done hold
Slack (hold path):      2.454ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/bl1/blt_state_FSM_FFd4 (FF)
  Destination:          AGNUS1/bl1/bltbold_init (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.808ns (Levels of Logic = 2)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/bl1/blt_state_FSM_FFd4 to AGNUS1/bl1/bltbold_init
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y20.XQ      Tcko                  0.576   AGNUS1/blt_state_FSM_FFd4
                                                       AGNUS1/bl1/blt_state_FSM_FFd4
    SLICE_X14Y23.G2      net (fanout=10)       0.557   AGNUS1/blt_state_FSM_FFd4
    SLICE_X14Y23.Y       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X14Y23.F3      net (fanout=3)        0.017   int3
    SLICE_X14Y23.X       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X15Y28.SR      net (fanout=2)        0.657   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X15Y28.CLK     Tcksr       (-Th)    -0.029   AGNUS1/bl1/bltbold_init
                                                       AGNUS1/bl1/bltbold_init
    -------------------------------------------------  ---------------------------
    Total                                      2.808ns (1.577ns logic, 1.231ns route)
                                                       (56.2% logic, 43.8% route)

--------------------------------------------------------------------------------


PAULA1/pi1/intreq_6: all setup
Slack (setup path):     11.431ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          PAULA1/pi1/intreq_6 (FF)
  Requirement:          35.243ns
  Data Path Delay:      23.458ns (Levels of Logic = 15)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to PAULA1/pi1/intreq_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y41.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.G2      net (fanout=1)        1.786   AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.Y       Tilo                  0.608   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X20Y31.F3      net (fanout=6)        0.024   AGNUS1/N1_0
    SLICE_X20Y31.X       Tilo                  0.608   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X20Y26.F4      net (fanout=30)       0.384   dma_spr
    SLICE_X20Y26.X       Tilo                  0.608   _l_data_2
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X22Y26.G2      net (fanout=29)       0.606   AGNUS1/N58
    SLICE_X22Y26.Y       Tilo                  0.608   DENISE1/sprm0/sps5/datla<13>
                                                       AGNUS1/dbr_and000073
    SLICE_X22Y26.F4      net (fanout=8)        0.040   AGNUS1/dbr_and0000
    SLICE_X22Y26.X       Tilo                  0.608   DENISE1/sprm0/sps5/datla<13>
                                                       AGNUS1/dbr
    SLICE_X30Y39.F4      net (fanout=38)       1.970   dbr
    SLICE_X30Y39.X       Tilo                  0.608   CPU1/enable114
                                                       CPU1/enable114
    SLICE_X30Y38.G2      net (fanout=2)        0.271   CPU1/enable114
    SLICE_X30Y38.Y       Tilo                  0.608   DENISE1/bplm0/bpl3dat<15>
                                                       CPU1/enable
    SLICE_X29Y36.G4      net (fanout=7)        0.387   enable
    SLICE_X29Y36.Y       Tilo                  0.551   DENISE1/bplm0/bpl6dat<13>
                                                       CPU1/rd1
    SLICE_X28Y31.G3      net (fanout=48)       1.926   cpu_rd
    SLICE_X28Y31.Y       Tilo                  0.608   AGNUS1/N31
                                                       AGNUS1/reg_address<1>1197
    SLICE_X28Y31.F1      net (fanout=1)        0.587   AGNUS1/reg_address<1>1197/O
    SLICE_X28Y31.X       Tilo                  0.608   AGNUS1/N31
                                                       AGNUS1/reg_address<1>11118
    SLICE_X29Y28.G3      net (fanout=9)        0.463   AGNUS1/N31
    SLICE_X29Y28.Y       Tilo                  0.551   PAULA1/N2
                                                       AGNUS1/reg_address<6>74
    SLICE_X32Y39.G2      net (fanout=32)       2.676   reg_address<6>
    SLICE_X32Y39.Y       Tilo                  0.608   USERIO1/osd1/t_ide_config<2>
                                                       PAULA1/pu1/data_out<13>11_SW0
    SLICE_X32Y39.F1      net (fanout=2)        0.590   PAULA1/pu1/N848
    SLICE_X32Y39.X       Tilo                  0.608   USERIO1/osd1/t_ide_config<2>
                                                       PAULA1/pi1/intena_cmp_eq00001
    SLICE_X34Y39.G2      net (fanout=5)        0.594   N2
    SLICE_X34Y39.Y       Tilo                  0.608   USERIO1/osd1/t_ide_config<0>
                                                       PAULA1/pi1/tmp_cmp_eq00001
    SLICE_X32Y32.G1      net (fanout=15)       1.346   PAULA1/pi1/tmp_cmp_eq0000
    SLICE_X32Y32.CLK     Tgck                  0.690   intreq_6
                                                       PAULA1/pi1/intreq_6_or00001
                                                       PAULA1/pi1/intreq_6
    -------------------------------------------------  ---------------------------
    Total                                     23.458ns (9.808ns logic, 13.650ns route)
                                                       (41.8% logic, 58.2% route)

--------------------------------------------------------------------------------


PAULA1/pi1/intreq_6: via_done setup
Slack (setup path):     20.535ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          PAULA1/pi1/intreq_6 (FF)
  Requirement:          35.243ns
  Data Path Delay:      14.354ns (Levels of Logic = 6)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to PAULA1/pi1/intreq_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y41.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.G2      net (fanout=1)        1.786   AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.Y       Tilo                  0.608   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X20Y31.F3      net (fanout=6)        0.024   AGNUS1/N1_0
    SLICE_X20Y31.X       Tilo                  0.608   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X20Y26.F4      net (fanout=30)       0.384   dma_spr
    SLICE_X20Y26.X       Tilo                  0.608   _l_data_2
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X22Y26.G2      net (fanout=29)       0.606   AGNUS1/N58
    SLICE_X22Y26.Y       Tilo                  0.608   DENISE1/sprm0/sps5/datla<13>
                                                       AGNUS1/dbr_and000073
    SLICE_X22Y11.G4      net (fanout=8)        1.313   AGNUS1/dbr_and0000
    SLICE_X22Y11.Y       Tilo                  0.608   DENISE1/sprm0/sps6/datla<13>
                                                       AGNUS1/address_out<10>111
    SLICE_X14Y23.G1      net (fanout=24)       2.057   N33_1
    SLICE_X14Y23.Y       Tilo                  0.608   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X32Y32.BY      net (fanout=3)        2.647   int3
    SLICE_X32Y32.CLK     Tsrck                 1.169   intreq_6
                                                       PAULA1/pi1/intreq_6
    -------------------------------------------------  ---------------------------
    Total                                     14.354ns (5.537ns logic, 8.817ns route)
                                                       (38.6% logic, 61.4% route)

--------------------------------------------------------------------------------


PAULA1/pi1/intreq_6: all hold
Slack (hold path):      1.231ns (requirement - (clock path skew + uncertainty - data path))
  Source:               PAULA1/pi1/intreq_6 (FF)
  Destination:          PAULA1/pi1/intreq_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.231ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: PAULA1/pi1/intreq_6 to PAULA1/pi1/intreq_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X32Y32.YQ      Tcko                  0.576   intreq_6
                                                       PAULA1/pi1/intreq_6
    SLICE_X32Y32.G2      net (fanout=3)        0.549   intreq_6
    SLICE_X32Y32.CLK     Tckg        (-Th)    -0.106   intreq_6
                                                       PAULA1/pi1/intreq_6_or00001
                                                       PAULA1/pi1/intreq_6
    -------------------------------------------------  ---------------------------
    Total                                      1.231ns (0.682ns logic, 0.549ns route)
                                                       (55.4% logic, 44.6% route)

--------------------------------------------------------------------------------



PAULA1/pi1/intreq_6: via_done hold
Slack (hold path):      3.525ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/bl1/blt_state_FSM_FFd4 (FF)
  Destination:          PAULA1/pi1/intreq_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.880ns (Levels of Logic = 1)
  Clock Path Skew:      0.001ns (0.437 - 0.436)
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/bl1/blt_state_FSM_FFd4 to PAULA1/pi1/intreq_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y20.XQ      Tcko                  0.576   AGNUS1/blt_state_FSM_FFd4
                                                       AGNUS1/bl1/blt_state_FSM_FFd4
    SLICE_X14Y23.G2      net (fanout=10)       0.557   AGNUS1/blt_state_FSM_FFd4
    SLICE_X14Y23.Y       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X32Y32.BY      net (fanout=3)        2.118   int3
    SLICE_X32Y32.CLK     Tcksr       (-Th)    -0.143   intreq_6
                                                       PAULA1/pi1/intreq_6
    -------------------------------------------------  ---------------------------
    Total                                      3.880ns (1.205ns logic, 2.675ns route)
                                                       (31.1% logic, 68.9% route)

--------------------------------------------------------------------------------


Related clk28 via_done: reported setup
Slack (setup path):     20.535ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          PAULA1/pi1/intreq_6 (FF)
  Requirement:          35.243ns
  Data Path Delay:      14.354ns (Levels of Logic = 6)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to PAULA1/pi1/intreq_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y41.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.G2      net (fanout=1)        1.786   AGNUS1/spr1/sprdmastate
    SLICE_X20Y31.Y       Tilo                  0.608   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X20Y31.F3      net (fanout=6)        0.024   AGNUS1/N1_0
    SLICE_X20Y31.X       Tilo                  0.608   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X20Y26.F4      net (fanout=30)       0.384   dma_spr
    SLICE_X20Y26.X       Tilo                  0.608   _l_data_2
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X22Y26.G2      net (fanout=29)       0.606   AGNUS1/N58
    SLICE_X22Y26.Y       Tilo                  0.608   DENISE1/sprm0/sps5/datla<13>
                                                       AGNUS1/dbr_and000073
    SLICE_X22Y11.G4      net (fanout=8)        1.313   AGNUS1/dbr_and0000
    SLICE_X22Y11.Y       Tilo                  0.608   DENISE1/sprm0/sps6/datla<13>
                                                       AGNUS1/address_out<10>111
    SLICE_X14Y23.G1      net (fanout=24)       2.057   N33_1
    SLICE_X14Y23.Y       Tilo                  0.608   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X32Y32.BY      net (fanout=3)        2.647   int3
    SLICE_X32Y32.CLK     Tsrck                 1.169   intreq_6
                                                       PAULA1/pi1/intreq_6
    -------------------------------------------------  ---------------------------
    Total                                     14.354ns (5.537ns logic, 8.817ns route)
                                                       (38.6% logic, 61.4% route)

--------------------------------------------------------------------------------


Related clk28 via_done: reported hold
Slack (hold path):      5.860ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/spr1/sprvstop (FF)
  Destination:          AGNUS1/bl1/busy (FF)
  Requirement:          -0.001ns
  Data Path Delay:      6.216ns (Levels of Logic = 5)
  Clock Path Skew:      0.001ns (1.843 - 1.842)
  Source Clock:         clk28m rising at 422.904ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/spr1/sprvstop to AGNUS1/bl1/busy
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y30.YQ      Tcko                  0.576   AGNUS1/sprvstop
                                                       AGNUS1/spr1/sprvstop
    SLICE_X20Y31.G3      net (fanout=2)        0.319   AGNUS1/sprvstop
    SLICE_X20Y31.Y       Tilo                  0.486   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X20Y31.F3      net (fanout=6)        0.019   AGNUS1/N1_0
    SLICE_X20Y31.X       Tilo                  0.486   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X20Y26.F4      net (fanout=30)       0.307   dma_spr
    SLICE_X20Y26.X       Tilo                  0.486   _l_data_2
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X21Y18.F4      net (fanout=29)       0.682   AGNUS1/N58
    SLICE_X21Y18.X       Tilo                  0.441   AGNUS1/cp1/cop1lch<17>
                                                       AGNUS1/bl1/done_SW1
    SLICE_X14Y23.G4      net (fanout=1)        1.365   AGNUS1/bl1/N1174
    SLICE_X14Y23.Y       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X16Y27.CE      net (fanout=3)        0.563   int3
    SLICE_X16Y27.CLK     Tckce       (-Th)     0.000   busy_0
                                                       AGNUS1/bl1/busy
    -------------------------------------------------  ---------------------------
    Total                                      6.216ns (2.961ns logic, 3.255ns route)
                                                       (47.6% logic, 52.4% route)

--------------------------------------------------------------------------------
