Timing constraint: TS_R3_LOCAL_COMPLETION = MAXDELAY FROM TIMEGRP 
"R3_LOCAL_ACK" TO TIMEGRP "R3_LOCAL_REQUEST" 1000 ns DATAPATHONLY;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   6.579ns.
--------------------------------------------------------------------------------

Paths for end point CPU1/l_as28m (SLICE_X41Y36.SR), 1 path
--------------------------------------------------------------------------------
Slack (setup paths):    993.421ns (requirement - (data path - clock path skew + uncertainty))
  Source:               CPU1/_ta_t1 (FF)
  Destination:          CPU1/l_as28m (FF)
  Requirement:          1000.000ns
  Data Path Delay:      6.579ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: CPU1/_ta_t1 to CPU1/l_as28m
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X37Y34.YQ      Tcko                  0.720   CPU1/_ta_t1
                                                       CPU1/_ta_t1
    SLICE_X45Y37.G1      net (fanout=2)        3.212   CPU1/_ta_t1
    SLICE_X45Y37.X       Tif5x                 0.911   CPU1/l_as28m_or000012
                                                       CPU1/l_as28m_or0000121
                                                       CPU1/l_as28m_or000012_f5
    SLICE_X41Y36.SR      net (fanout=1)        0.710   CPU1/l_as28m_or000012
    SLICE_X41Y36.CLK     Tsrck                 1.026   CPU1/l_as28m
                                                       CPU1/l_as28m
    -------------------------------------------------  ---------------------------
    Total                                      6.579ns (2.657ns logic, 3.922ns route)
                                                       (40.4% logic, 59.6% route)

--------------------------------------------------------------------------------

Fastest Paths: TS_R3_LOCAL_COMPLETION = MAXDELAY FROM TIMEGRP "R3_LOCAL_ACK" TO TIMEGRP "R3_LOCAL_REQUEST" 1000 ns DATAPATHONLY;
--------------------------------------------------------------------------------

Paths for end point CPU1/l_as28m (SLICE_X41Y36.SR), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      4.472ns (requirement - (clock path skew + uncertainty - data path))
  Source:               CPU1/_ta_t1 (FF)
  Destination:          CPU1/l_as28m (FF)
  Requirement:          0.000ns
  Data Path Delay:      4.472ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 422.904ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: CPU1/_ta_t1 to CPU1/l_as28m
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X37Y34.YQ      Tcko                  0.576   CPU1/_ta_t1
                                                       CPU1/_ta_t1
    SLICE_X45Y37.G1      net (fanout=2)        2.570   CPU1/_ta_t1
    SLICE_X45Y37.X       Tif5x                 0.729   CPU1/l_as28m_or000012
                                                       CPU1/l_as28m_or0000121
                                                       CPU1/l_as28m_or000012_f5
    SLICE_X41Y36.SR      net (fanout=1)        0.568   CPU1/l_as28m_or000012
    SLICE_X41Y36.CLK     Tcksr       (-Th)    -0.029   CPU1/l_as28m
                                                       CPU1/l_as28m
    -------------------------------------------------  ---------------------------
    Total                                      4.472ns (1.334ns logic, 3.138ns route)
                                                       (29.8% logic, 70.2% route)

--------------------------------------------------------------------------------

================================================================================

Timing constraint: TS_R3_FIRST_SYNC = MAXDELAY FROM TIMEGRP "R3_LOCAL_ACK" TO 
TIMEGRP "R3_CPU_SYNC1" 1000 ns DATAPATHONLY;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   3.186ns.
--------------------------------------------------------------------------------

Paths for end point CPU1/_ta_t2 (SLICE_X45Y38.CE), 1 path
--------------------------------------------------------------------------------
Slack (setup paths):    996.814ns (requirement - (data path - clock path skew + uncertainty))
  Source:               CPU1/_ta_t1 (FF)
  Destination:          CPU1/_ta_t2 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      3.186ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising
  Destination Clock:    cpu_clk_OBUF rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: CPU1/_ta_t1 to CPU1/_ta_t2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X37Y34.YQ      Tcko                  0.720   CPU1/_ta_t1
                                                       CPU1/_ta_t1
    SLICE_X45Y38.CE      net (fanout=2)        1.864   CPU1/_ta_t1
    SLICE_X45Y38.CLK     Tceck                 0.602   CPU1/_ta_t2
                                                       CPU1/_ta_t2
    -------------------------------------------------  ---------------------------
    Total                                      3.186ns (1.322ns logic, 1.864ns route)
                                                       (41.5% logic, 58.5% route)

--------------------------------------------------------------------------------

Fastest Paths: TS_R3_FIRST_SYNC = MAXDELAY FROM TIMEGRP "R3_LOCAL_ACK" TO TIMEGRP "R3_CPU_SYNC1" 1000 ns DATAPATHONLY;
--------------------------------------------------------------------------------

Paths for end point CPU1/_ta_t2 (SLICE_X45Y38.CE), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      2.067ns (requirement - (clock path skew + uncertainty - data path))
  Source:               CPU1/_ta_t1 (FF)
  Destination:          CPU1/_ta_t2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.067ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising
  Destination Clock:    cpu_clk_OBUF rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: CPU1/_ta_t1 to CPU1/_ta_t2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X37Y34.YQ      Tcko                  0.576   CPU1/_ta_t1
                                                       CPU1/_ta_t1
    SLICE_X45Y38.CE      net (fanout=2)        1.491   CPU1/_ta_t1
    SLICE_X45Y38.CLK     Tckce       (-Th)     0.000   CPU1/_ta_t2
                                                       CPU1/_ta_t2
    -------------------------------------------------  ---------------------------
    Total                                      2.067ns (0.576ns logic, 1.491ns route)
                                                       (27.9% logic, 72.1% route)

--------------------------------------------------------------------------------

================================================================================

Timing constraint: TS_R3_SECOND_SYNC = MAXDELAY FROM TIMEGRP "R3_CPU_SYNC1" TO 
TIMEGRP "R3_CPU_SYNC2" 1000 ns DATAPATHONLY;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   2.311ns.
--------------------------------------------------------------------------------

Paths for end point CPU1/_ta_t (SLICE_X45Y40.CE), 1 path
--------------------------------------------------------------------------------
Slack (setup paths):    997.689ns (requirement - (data path - clock path skew + uncertainty))
  Source:               CPU1/_ta_t2 (FF)
  Destination:          CPU1/_ta_t (FF)
  Requirement:          1000.000ns
  Data Path Delay:      2.311ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         cpu_clk_OBUF rising at 0.000ns
  Destination Clock:    cpu_clk_OBUF rising at 16.584ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: CPU1/_ta_t2 to CPU1/_ta_t
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X45Y38.YQ      Tcko                  0.720   CPU1/_ta_t2
                                                       CPU1/_ta_t2
    SLICE_X45Y40.CE      net (fanout=1)        0.989   CPU1/_ta_t2
    SLICE_X45Y40.CLK     Tceck                 0.602   CPU1/_ta_t
                                                       CPU1/_ta_t
    -------------------------------------------------  ---------------------------
    Total                                      2.311ns (1.322ns logic, 0.989ns route)
                                                       (57.2% logic, 42.8% route)

--------------------------------------------------------------------------------

Fastest Paths: TS_R3_SECOND_SYNC = MAXDELAY FROM TIMEGRP "R3_CPU_SYNC1" TO TIMEGRP "R3_CPU_SYNC2" 1000 ns DATAPATHONLY;
--------------------------------------------------------------------------------

Paths for end point CPU1/_ta_t (SLICE_X45Y40.CE), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      1.367ns (requirement - (clock path skew + uncertainty - data path))
  Source:               CPU1/_ta_t2 (FF)
  Destination:          CPU1/_ta_t (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.367ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         cpu_clk_OBUF rising at 0.000ns
  Destination Clock:    cpu_clk_OBUF rising at 0.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: CPU1/_ta_t2 to CPU1/_ta_t
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X45Y38.YQ      Tcko                  0.576   CPU1/_ta_t2
                                                       CPU1/_ta_t2
    SLICE_X45Y40.CE      net (fanout=1)        0.791   CPU1/_ta_t2
    SLICE_X45Y40.CLK     Tckce       (-Th)     0.000   CPU1/_ta_t
                                                       CPU1/_ta_t
    -------------------------------------------------  ---------------------------
    Total                                      1.367ns (0.576ns logic, 0.791ns route)
                                                       (42.1% logic, 57.9% route)

--------------------------------------------------------------------------------

================================================================================

Timing constraint: TS_R3_RETURN_ACK = MAXDELAY FROM TIMEGRP "R3_CPU_SYNC2" TO 
TIMEGRP "R3_CPU_FEEDBACK" 1000 ns DATAPATHONLY;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   1.821ns.
--------------------------------------------------------------------------------

Paths for end point CPU1/l_dtack (SLICE_X45Y39.F3), 1 path
--------------------------------------------------------------------------------
Slack (setup paths):    998.179ns (requirement - (data path - clock path skew + uncertainty))
  Source:               CPU1/_ta_t (FF)
  Destination:          CPU1/l_dtack (FF)
  Requirement:          1000.000ns
  Data Path Delay:      1.821ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         cpu_clk_OBUF rising
  Destination Clock:    clk rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: CPU1/_ta_t to CPU1/l_dtack
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X45Y40.YQ      Tcko                  0.720   CPU1/_ta_t
                                                       CPU1/_ta_t
    SLICE_X45Y39.F3      net (fanout=3)        0.468   CPU1/_ta_t
    SLICE_X45Y39.CLK     Tfck                  0.633   l_dtack
                                                       CPU1/private_internal_dtack
                                                       CPU1/l_dtack
    -------------------------------------------------  ---------------------------
    Total                                      1.821ns (1.353ns logic, 0.468ns route)
                                                       (74.3% logic, 25.7% route)

--------------------------------------------------------------------------------

Fastest Paths: TS_R3_RETURN_ACK = MAXDELAY FROM TIMEGRP "R3_CPU_SYNC2" TO TIMEGRP "R3_CPU_FEEDBACK" 1000 ns DATAPATHONLY;
--------------------------------------------------------------------------------

Paths for end point CPU1/l_dtack (SLICE_X45Y39.F3), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      1.012ns (requirement - (clock path skew + uncertainty - data path))
  Source:               CPU1/_ta_t (FF)
  Destination:          CPU1/l_dtack (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.012ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         cpu_clk_OBUF rising
  Destination Clock:    clk rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: CPU1/_ta_t to CPU1/l_dtack
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X45Y40.YQ      Tcko                  0.576   CPU1/_ta_t
                                                       CPU1/_ta_t
    SLICE_X45Y39.F3      net (fanout=3)        0.375   CPU1/_ta_t
    SLICE_X45Y39.CLK     Tckf        (-Th)    -0.061   l_dtack
                                                       CPU1/private_internal_dtack
                                                       CPU1/l_dtack
    -------------------------------------------------  ---------------------------
    Total                                      1.012ns (0.637ns logic, 0.375ns route)
                                                       (62.9% logic, 37.1% route)

--------------------------------------------------------------------------------

================================================================================

Timing constraint: TS_R3_CUSTOM_DATA = MAXDELAY FROM TIMEGRP "CPU_DATA" TO 
TIMEGRP "R3_CUSTOM_MASKS" 1000 ns DATAPATHONLY;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 32 paths analyzed, 32 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is  15.354ns.
--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_12 (SLICE_X48Y34.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  984.646ns (requirement - data path)
  Source:               cpu_data<12> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_12 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      15.354ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<12> to AGNUS1/bl1/bltafwm_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P141.I               Tiopi                 1.918   cpu_data<12>
                                                       cpu_data<12>
                                                       cpu_data_12_IOBUF/IBUF
    SLICE_X22Y14.F3      net (fanout=23)       5.292   N949
    SLICE_X22Y14.X       Tilo                  0.608   AGNUS1/bpd1/dmaena_delayed<0>
                                                       gary_cpu_data_in<12>1
    SLICE_X17Y19.F3      net (fanout=4)        1.499   gary_cpu_data_in<12>
    SLICE_X17Y19.X       Tilo                  0.551   AGNUS1/bl1/height<12>
                                                       GARY1/custom_data_in<12>1
    SLICE_X48Y34.BX      net (fanout=70)       5.283   custom_data_in<12>
    SLICE_X48Y34.CLK     Tdick                 0.203   AGNUS1/bl1/bltafwm<12>
                                                       AGNUS1/bl1/bltafwm_12
    -------------------------------------------------  ---------------------------
    Total                                     15.354ns (3.280ns logic, 12.074ns route)
                                                       (21.4% logic, 78.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_12 (SLICE_X45Y30.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  985.493ns (requirement - data path)
  Source:               cpu_data<12> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_12 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      14.507ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<12> to AGNUS1/bl1/bltalwm_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P141.I               Tiopi                 1.918   cpu_data<12>
                                                       cpu_data<12>
                                                       cpu_data_12_IOBUF/IBUF
    SLICE_X22Y14.F3      net (fanout=23)       5.292   N949
    SLICE_X22Y14.X       Tilo                  0.608   AGNUS1/bpd1/dmaena_delayed<0>
                                                       gary_cpu_data_in<12>1
    SLICE_X17Y19.F3      net (fanout=4)        1.499   gary_cpu_data_in<12>
    SLICE_X17Y19.X       Tilo                  0.551   AGNUS1/bl1/height<12>
                                                       GARY1/custom_data_in<12>1
    SLICE_X45Y30.BX      net (fanout=70)       4.436   custom_data_in<12>
    SLICE_X45Y30.CLK     Tdick                 0.203   AGNUS1/bl1/bltalwm<12>
                                                       AGNUS1/bl1/bltalwm_12
    -------------------------------------------------  ---------------------------
    Total                                     14.507ns (3.280ns logic, 11.227ns route)
                                                       (22.6% logic, 77.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_11 (SLICE_X46Y28.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  985.605ns (requirement - data path)
  Source:               cpu_data<11> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_11 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      14.395ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<11> to AGNUS1/bl1/bltalwm_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P144.I               Tiopi                 1.918   cpu_data<11>
                                                       cpu_data<11>
                                                       cpu_data_11_IOBUF/IBUF
    SLICE_X24Y15.G1      net (fanout=21)       4.197   N950
    SLICE_X24Y15.Y       Tilo                  0.608   _l_data_12
                                                       gary_cpu_data_in<11>1
    SLICE_X17Y11.F2      net (fanout=3)        2.519   gary_cpu_data_in<11>
    SLICE_X17Y11.X       Tilo                  0.551   AGNUS1/bl1/height<11>
                                                       GARY1/custom_data_in<11>1
    SLICE_X46Y28.BY      net (fanout=72)       4.341   custom_data_in<11>
    SLICE_X46Y28.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<10>
                                                       AGNUS1/bl1/bltalwm_11
    -------------------------------------------------  ---------------------------
    Total                                     14.395ns (3.338ns logic, 11.057ns route)
                                                       (23.2% logic, 76.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_13 (SLICE_X48Y34.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  985.717ns (requirement - data path)
  Source:               cpu_data<13> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_13 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      14.283ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<13> to AGNUS1/bl1/bltafwm_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P139.I               Tiopi                 1.918   cpu_data<13>
                                                       cpu_data<13>
                                                       cpu_data_13_IOBUF/IBUF
    SLICE_X23Y19.F1      net (fanout=21)       4.923   N948
    SLICE_X23Y19.X       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<13>
                                                       gary_cpu_data_in<13>1
    SLICE_X18Y16.F3      net (fanout=4)        1.544   gary_cpu_data_in<13>
    SLICE_X18Y16.X       Tilo                  0.608   AGNUS1/bl1/height<13>
                                                       GARY1/custom_data_in<13>1
    SLICE_X48Y34.BY      net (fanout=70)       4.478   custom_data_in<13>
    SLICE_X48Y34.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<12>
                                                       AGNUS1/bl1/bltafwm_13
    -------------------------------------------------  ---------------------------
    Total                                     14.283ns (3.338ns logic, 10.945ns route)
                                                       (23.4% logic, 76.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_11 (SLICE_X48Y32.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  985.745ns (requirement - data path)
  Source:               cpu_data<11> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_11 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      14.255ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<11> to AGNUS1/bl1/bltafwm_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P144.I               Tiopi                 1.918   cpu_data<11>
                                                       cpu_data<11>
                                                       cpu_data_11_IOBUF/IBUF
    SLICE_X24Y15.G1      net (fanout=21)       4.197   N950
    SLICE_X24Y15.Y       Tilo                  0.608   _l_data_12
                                                       gary_cpu_data_in<11>1
    SLICE_X17Y11.F2      net (fanout=3)        2.519   gary_cpu_data_in<11>
    SLICE_X17Y11.X       Tilo                  0.551   AGNUS1/bl1/height<11>
                                                       GARY1/custom_data_in<11>1
    SLICE_X48Y32.BY      net (fanout=72)       4.201   custom_data_in<11>
    SLICE_X48Y32.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<10>
                                                       AGNUS1/bl1/bltafwm_11
    -------------------------------------------------  ---------------------------
    Total                                     14.255ns (3.338ns logic, 10.917ns route)
                                                       (23.4% logic, 76.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_8 (SLICE_X41Y28.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  986.238ns (requirement - data path)
  Source:               cpu_data<8> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_8 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      13.762ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<8> to AGNUS1/bl1/bltalwm_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P152.I               Tiopi                 1.918   cpu_data<8>
                                                       cpu_data<8>
                                                       cpu_data_8_IOBUF/IBUF
    SLICE_X27Y14.G1      net (fanout=22)       6.265   N953
    SLICE_X27Y14.Y       Tilo                  0.551   _l_data_11
                                                       gary_cpu_data_in<8>1
    SLICE_X29Y15.F2      net (fanout=3)        0.600   gary_cpu_data_in<8>
    SLICE_X29Y15.X       Tilo                  0.551   AGNUS1/bl1/bltadat<8>
                                                       GARY1/custom_data_in<8>1
    SLICE_X41Y28.BY      net (fanout=72)       3.616   custom_data_in<8>
    SLICE_X41Y28.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<8>
                                                       AGNUS1/bl1/bltalwm_8
    -------------------------------------------------  ---------------------------
    Total                                     13.762ns (3.281ns logic, 10.481ns route)
                                                       (23.8% logic, 76.2% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_8 (SLICE_X47Y31.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  986.267ns (requirement - data path)
  Source:               cpu_data<8> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_8 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      13.733ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<8> to AGNUS1/bl1/bltafwm_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P152.I               Tiopi                 1.918   cpu_data<8>
                                                       cpu_data<8>
                                                       cpu_data_8_IOBUF/IBUF
    SLICE_X27Y14.G1      net (fanout=22)       6.265   N953
    SLICE_X27Y14.Y       Tilo                  0.551   _l_data_11
                                                       gary_cpu_data_in<8>1
    SLICE_X29Y15.F2      net (fanout=3)        0.600   gary_cpu_data_in<8>
    SLICE_X29Y15.X       Tilo                  0.551   AGNUS1/bl1/bltadat<8>
                                                       GARY1/custom_data_in<8>1
    SLICE_X47Y31.BX      net (fanout=72)       3.645   custom_data_in<8>
    SLICE_X47Y31.CLK     Tdick                 0.203   AGNUS1/bl1/bltafwm<8>
                                                       AGNUS1/bl1/bltafwm_8
    -------------------------------------------------  ---------------------------
    Total                                     13.733ns (3.223ns logic, 10.510ns route)
                                                       (23.5% logic, 76.5% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_10 (SLICE_X46Y28.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  986.571ns (requirement - data path)
  Source:               cpu_data<10> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_10 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      13.429ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<10> to AGNUS1/bl1/bltalwm_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P147.I               Tiopi                 1.918   cpu_data<10>
                                                       cpu_data<10>
                                                       cpu_data_10_IOBUF/IBUF
    SLICE_X24Y15.F3      net (fanout=22)       4.459   N951
    SLICE_X24Y15.X       Tilo                  0.608   _l_data_12
                                                       gary_cpu_data_in<10>1
    SLICE_X17Y15.F1      net (fanout=3)        2.323   gary_cpu_data_in<10>
    SLICE_X17Y15.X       Tilo                  0.551   AGNUS1/bl1/height<10>
                                                       GARY1/custom_data_in<10>1
    SLICE_X46Y28.BX      net (fanout=75)       3.367   custom_data_in<10>
    SLICE_X46Y28.CLK     Tdick                 0.203   AGNUS1/bl1/bltalwm<10>
                                                       AGNUS1/bl1/bltalwm_10
    -------------------------------------------------  ---------------------------
    Total                                     13.429ns (3.280ns logic, 10.149ns route)
                                                       (24.4% logic, 75.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_13 (SLICE_X45Y30.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  986.651ns (requirement - data path)
  Source:               cpu_data<13> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_13 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      13.349ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<13> to AGNUS1/bl1/bltalwm_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P139.I               Tiopi                 1.918   cpu_data<13>
                                                       cpu_data<13>
                                                       cpu_data_13_IOBUF/IBUF
    SLICE_X23Y19.F1      net (fanout=21)       4.923   N948
    SLICE_X23Y19.X       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<13>
                                                       gary_cpu_data_in<13>1
    SLICE_X18Y16.F3      net (fanout=4)        1.544   gary_cpu_data_in<13>
    SLICE_X18Y16.X       Tilo                  0.608   AGNUS1/bl1/height<13>
                                                       GARY1/custom_data_in<13>1
    SLICE_X45Y30.BY      net (fanout=70)       3.544   custom_data_in<13>
    SLICE_X45Y30.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<12>
                                                       AGNUS1/bl1/bltalwm_13
    -------------------------------------------------  ---------------------------
    Total                                     13.349ns (3.338ns logic, 10.011ns route)
                                                       (25.0% logic, 75.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_10 (SLICE_X48Y32.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  986.668ns (requirement - data path)
  Source:               cpu_data<10> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_10 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      13.332ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<10> to AGNUS1/bl1/bltafwm_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P147.I               Tiopi                 1.918   cpu_data<10>
                                                       cpu_data<10>
                                                       cpu_data_10_IOBUF/IBUF
    SLICE_X24Y15.F3      net (fanout=22)       4.459   N951
    SLICE_X24Y15.X       Tilo                  0.608   _l_data_12
                                                       gary_cpu_data_in<10>1
    SLICE_X17Y15.F1      net (fanout=3)        2.323   gary_cpu_data_in<10>
    SLICE_X17Y15.X       Tilo                  0.551   AGNUS1/bl1/height<10>
                                                       GARY1/custom_data_in<10>1
    SLICE_X48Y32.BX      net (fanout=75)       3.270   custom_data_in<10>
    SLICE_X48Y32.CLK     Tdick                 0.203   AGNUS1/bl1/bltafwm<10>
                                                       AGNUS1/bl1/bltafwm_10
    -------------------------------------------------  ---------------------------
    Total                                     13.332ns (3.280ns logic, 10.052ns route)
                                                       (24.6% logic, 75.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_9 (SLICE_X47Y31.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  986.672ns (requirement - data path)
  Source:               cpu_data<9> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_9 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      13.328ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<9> to AGNUS1/bl1/bltafwm_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P149.I               Tiopi                 1.918   cpu_data<9>
                                                       cpu_data<9>
                                                       cpu_data_9_IOBUF/IBUF
    SLICE_X26Y14.F4      net (fanout=22)       4.669   N952
    SLICE_X26Y14.X       Tilo                  0.608   DENISE1/sprm0/sps2/datlb<10>
                                                       gary_cpu_data_in<9>1
    SLICE_X27Y21.F1      net (fanout=3)        2.859   gary_cpu_data_in<9>
    SLICE_X27Y21.X       Tilo                  0.551   AGNUS1/bl1/bltadat<9>
                                                       GARY1/custom_data_in<9>1
    SLICE_X47Y31.BY      net (fanout=73)       2.462   custom_data_in<9>
    SLICE_X47Y31.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<8>
                                                       AGNUS1/bl1/bltafwm_9
    -------------------------------------------------  ---------------------------
    Total                                     13.328ns (3.338ns logic, 9.990ns route)
                                                       (25.0% logic, 75.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_5 (SLICE_X44Y28.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  986.808ns (requirement - data path)
  Source:               cpu_data<5> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_5 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      13.192ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<5> to AGNUS1/bl1/bltalwm_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P165.I               Tiopi                 1.918   cpu_data<5>
                                                       cpu_data<5>
                                                       cpu_data_5_IOBUF/IBUF
    SLICE_X36Y16.G2      net (fanout=19)       3.913   N956
    SLICE_X36Y16.Y       Tilo                  0.608   AGNUS1/cp1/ir2<11>
                                                       gary_cpu_data_in<5>1
    SLICE_X28Y16.F3      net (fanout=4)        2.156   gary_cpu_data_in<5>
    SLICE_X28Y16.X       Tilo                  0.608   AGNUS1/bl1/bltadat<5>
                                                       GARY1/custom_data_in<5>1
    SLICE_X44Y28.BX      net (fanout=89)       3.786   custom_data_in<5>
    SLICE_X44Y28.CLK     Tdick                 0.203   AGNUS1/bl1/bltalwm<5>
                                                       AGNUS1/bl1/bltalwm_5
    -------------------------------------------------  ---------------------------
    Total                                     13.192ns (3.337ns logic, 9.855ns route)
                                                       (25.3% logic, 74.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_9 (SLICE_X44Y28.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  987.023ns (requirement - data path)
  Source:               cpu_data<9> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_9 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      12.977ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<9> to AGNUS1/bl1/bltalwm_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P149.I               Tiopi                 1.918   cpu_data<9>
                                                       cpu_data<9>
                                                       cpu_data_9_IOBUF/IBUF
    SLICE_X26Y14.F4      net (fanout=22)       4.669   N952
    SLICE_X26Y14.X       Tilo                  0.608   DENISE1/sprm0/sps2/datlb<10>
                                                       gary_cpu_data_in<9>1
    SLICE_X27Y21.F1      net (fanout=3)        2.859   gary_cpu_data_in<9>
    SLICE_X27Y21.X       Tilo                  0.551   AGNUS1/bl1/bltadat<9>
                                                       GARY1/custom_data_in<9>1
    SLICE_X44Y28.BY      net (fanout=73)       2.111   custom_data_in<9>
    SLICE_X44Y28.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<5>
                                                       AGNUS1/bl1/bltalwm_9
    -------------------------------------------------  ---------------------------
    Total                                     12.977ns (3.338ns logic, 9.639ns route)
                                                       (25.7% logic, 74.3% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_5 (SLICE_X45Y24.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  987.109ns (requirement - data path)
  Source:               cpu_data<5> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_5 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      12.891ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<5> to AGNUS1/bl1/bltafwm_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P165.I               Tiopi                 1.918   cpu_data<5>
                                                       cpu_data<5>
                                                       cpu_data_5_IOBUF/IBUF
    SLICE_X36Y16.G2      net (fanout=19)       3.913   N956
    SLICE_X36Y16.Y       Tilo                  0.608   AGNUS1/cp1/ir2<11>
                                                       gary_cpu_data_in<5>1
    SLICE_X28Y16.F3      net (fanout=4)        2.156   gary_cpu_data_in<5>
    SLICE_X28Y16.X       Tilo                  0.608   AGNUS1/bl1/bltadat<5>
                                                       GARY1/custom_data_in<5>1
    SLICE_X45Y24.BY      net (fanout=89)       3.427   custom_data_in<5>
    SLICE_X45Y24.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<4>
                                                       AGNUS1/bl1/bltafwm_5
    -------------------------------------------------  ---------------------------
    Total                                     12.891ns (3.395ns logic, 9.496ns route)
                                                       (26.3% logic, 73.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_3 (SLICE_X42Y29.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  987.540ns (requirement - data path)
  Source:               cpu_data<3> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_3 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      12.460ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<3> to AGNUS1/bl1/bltafwm_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P162.I               Tiopi                 1.918   cpu_data<3>
                                                       cpu_data<3>
                                                       cpu_data_3_IOBUF/IBUF
    SLICE_X36Y21.F2      net (fanout=20)       5.190   N958
    SLICE_X36Y21.X       Tilo                  0.608   _l_data_3
                                                       gary_cpu_data_in<3>1
    SLICE_X30Y25.G1      net (fanout=5)        1.893   gary_cpu_data_in<3>
    SLICE_X30Y25.Y       Tilo                  0.608   AGNUS1/bl1/bltadat<3>
                                                       GARY1/custom_data_in<3>1
    SLICE_X42Y29.BX      net (fanout=93)       2.040   custom_data_in<3>
    SLICE_X42Y29.CLK     Tdick                 0.203   AGNUS1/bl1/bltafwm<3>
                                                       AGNUS1/bl1/bltafwm_3
    -------------------------------------------------  ---------------------------
    Total                                     12.460ns (3.337ns logic, 9.123ns route)
                                                       (26.8% logic, 73.2% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_15 (SLICE_X49Y33.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  987.706ns (requirement - data path)
  Source:               cpu_data<15> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_15 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      12.294ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<15> to AGNUS1/bl1/bltalwm_15
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P135.I               Tiopi                 1.918   cpu_data<15>
                                                       cpu_data<15>
                                                       cpu_data_15_IOBUF/IBUF
    SLICE_X29Y16.F2      net (fanout=27)       4.198   N946
    SLICE_X29Y16.X       Tilo                  0.551   gary_cpu_data_in<15>
                                                       gary_cpu_data_in<15>1
    SLICE_X20Y22.F3      net (fanout=5)        1.326   gary_cpu_data_in<15>
    SLICE_X20Y22.X       Tilo                  0.608   AGNUS1/bpd1/vdiwstop<7>
                                                       GARY1/custom_data_in<15>1
    SLICE_X49Y33.BY      net (fanout=131)      3.432   custom_data_in<15>
    SLICE_X49Y33.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<15>
                                                       AGNUS1/bl1/bltalwm_15
    -------------------------------------------------  ---------------------------
    Total                                     12.294ns (3.338ns logic, 8.956ns route)
                                                       (27.2% logic, 72.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_3 (SLICE_X45Y26.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  987.940ns (requirement - data path)
  Source:               cpu_data<3> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_3 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      12.060ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<3> to AGNUS1/bl1/bltalwm_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P162.I               Tiopi                 1.918   cpu_data<3>
                                                       cpu_data<3>
                                                       cpu_data_3_IOBUF/IBUF
    SLICE_X36Y21.F2      net (fanout=20)       5.190   N958
    SLICE_X36Y21.X       Tilo                  0.608   _l_data_3
                                                       gary_cpu_data_in<3>1
    SLICE_X30Y25.G1      net (fanout=5)        1.893   gary_cpu_data_in<3>
    SLICE_X30Y25.Y       Tilo                  0.608   AGNUS1/bl1/bltadat<3>
                                                       GARY1/custom_data_in<3>1
    SLICE_X45Y26.BY      net (fanout=93)       1.582   custom_data_in<3>
    SLICE_X45Y26.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<2>
                                                       AGNUS1/bl1/bltalwm_3
    -------------------------------------------------  ---------------------------
    Total                                     12.060ns (3.395ns logic, 8.665ns route)
                                                       (28.2% logic, 71.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_2 (SLICE_X45Y26.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  987.949ns (requirement - data path)
  Source:               cpu_data<2> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_2 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      12.051ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<2> to AGNUS1/bl1/bltalwm_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P156.I               Tiopi                 1.918   cpu_data<2>
                                                       cpu_data<2>
                                                       cpu_data_2_IOBUF/IBUF
    SLICE_X24Y23.F3      net (fanout=20)       5.437   N959
    SLICE_X24Y23.X       Tilo                  0.608   gary_cpu_data_in<2>
                                                       gary_cpu_data_in<2>1
    SLICE_X24Y27.F1      net (fanout=3)        0.932   gary_cpu_data_in<2>
    SLICE_X24Y27.X       Tilo                  0.608   AGNUS1/bl1/bltadat<2>
                                                       GARY1/custom_data_in<2>1
    SLICE_X45Y26.BX      net (fanout=99)       2.345   custom_data_in<2>
    SLICE_X45Y26.CLK     Tdick                 0.203   AGNUS1/bl1/bltalwm<2>
                                                       AGNUS1/bl1/bltalwm_2
    -------------------------------------------------  ---------------------------
    Total                                     12.051ns (3.337ns logic, 8.714ns route)
                                                       (27.7% logic, 72.3% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_15 (SLICE_X49Y31.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.059ns (requirement - data path)
  Source:               cpu_data<15> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_15 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.941ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<15> to AGNUS1/bl1/bltafwm_15
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P135.I               Tiopi                 1.918   cpu_data<15>
                                                       cpu_data<15>
                                                       cpu_data_15_IOBUF/IBUF
    SLICE_X29Y16.F2      net (fanout=27)       4.198   N946
    SLICE_X29Y16.X       Tilo                  0.551   gary_cpu_data_in<15>
                                                       gary_cpu_data_in<15>1
    SLICE_X20Y22.F3      net (fanout=5)        1.326   gary_cpu_data_in<15>
    SLICE_X20Y22.X       Tilo                  0.608   AGNUS1/bpd1/vdiwstop<7>
                                                       GARY1/custom_data_in<15>1
    SLICE_X49Y31.BY      net (fanout=131)      3.079   custom_data_in<15>
    SLICE_X49Y31.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<14>
                                                       AGNUS1/bl1/bltafwm_15
    -------------------------------------------------  ---------------------------
    Total                                     11.941ns (3.338ns logic, 8.603ns route)
                                                       (28.0% logic, 72.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_7 (SLICE_X41Y27.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.080ns (requirement - data path)
  Source:               cpu_data<7> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_7 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.920ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<7> to AGNUS1/bl1/bltafwm_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P155.I               Tiopi                 1.918   cpu_data<7>
                                                       cpu_data<7>
                                                       cpu_data_7_IOBUF/IBUF
    SLICE_X29Y16.G3      net (fanout=22)       5.420   N954
    SLICE_X29Y16.Y       Tilo                  0.551   gary_cpu_data_in<15>
                                                       gary_cpu_data_in<7>1
    SLICE_X30Y21.F2      net (fanout=5)        1.229   gary_cpu_data_in<7>
    SLICE_X30Y21.X       Tilo                  0.608   AGNUS1/bl1/bltadat<7>
                                                       GARY1/custom_data_in<7>1
    SLICE_X41Y27.BY      net (fanout=84)       1.933   custom_data_in<7>
    SLICE_X41Y27.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<7>
                                                       AGNUS1/bl1/bltafwm_7
    -------------------------------------------------  ---------------------------
    Total                                     11.920ns (3.338ns logic, 8.582ns route)
                                                       (28.0% logic, 72.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_7 (SLICE_X36Y29.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.082ns (requirement - data path)
  Source:               cpu_data<7> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_7 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.918ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<7> to AGNUS1/bl1/bltalwm_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P155.I               Tiopi                 1.918   cpu_data<7>
                                                       cpu_data<7>
                                                       cpu_data_7_IOBUF/IBUF
    SLICE_X29Y16.G3      net (fanout=22)       5.420   N954
    SLICE_X29Y16.Y       Tilo                  0.551   gary_cpu_data_in<15>
                                                       gary_cpu_data_in<7>1
    SLICE_X30Y21.F2      net (fanout=5)        1.229   gary_cpu_data_in<7>
    SLICE_X30Y21.X       Tilo                  0.608   AGNUS1/bl1/bltadat<7>
                                                       GARY1/custom_data_in<7>1
    SLICE_X36Y29.BY      net (fanout=84)       1.931   custom_data_in<7>
    SLICE_X36Y29.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<6>
                                                       AGNUS1/bl1/bltalwm_7
    -------------------------------------------------  ---------------------------
    Total                                     11.918ns (3.338ns logic, 8.580ns route)
                                                       (28.0% logic, 72.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_2 (SLICE_X43Y26.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.093ns (requirement - data path)
  Source:               cpu_data<2> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_2 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.907ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<2> to AGNUS1/bl1/bltafwm_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P156.I               Tiopi                 1.918   cpu_data<2>
                                                       cpu_data<2>
                                                       cpu_data_2_IOBUF/IBUF
    SLICE_X24Y23.F3      net (fanout=20)       5.437   N959
    SLICE_X24Y23.X       Tilo                  0.608   gary_cpu_data_in<2>
                                                       gary_cpu_data_in<2>1
    SLICE_X24Y27.F1      net (fanout=3)        0.932   gary_cpu_data_in<2>
    SLICE_X24Y27.X       Tilo                  0.608   AGNUS1/bl1/bltadat<2>
                                                       GARY1/custom_data_in<2>1
    SLICE_X43Y26.BY      net (fanout=99)       2.143   custom_data_in<2>
    SLICE_X43Y26.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<2>
                                                       AGNUS1/bl1/bltafwm_2
    -------------------------------------------------  ---------------------------
    Total                                     11.907ns (3.395ns logic, 8.512ns route)
                                                       (28.5% logic, 71.5% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_6 (SLICE_X42Y29.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.326ns (requirement - data path)
  Source:               cpu_data<6> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_6 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.674ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<6> to AGNUS1/bl1/bltafwm_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P161.I               Tiopi                 1.918   cpu_data<6>
                                                       cpu_data<6>
                                                       cpu_data_6_IOBUF/IBUF
    SLICE_X34Y17.F2      net (fanout=19)       5.189   N955
    SLICE_X34Y17.X       Tilo                  0.608   MIA1/spi_rx_data<0>
                                                       gary_cpu_data_in<6>1
    SLICE_X27Y17.F3      net (fanout=4)        0.907   gary_cpu_data_in<6>
    SLICE_X27Y17.X       Tilo                  0.551   AGNUS1/bl1/bltadat<6>
                                                       GARY1/custom_data_in<6>1
    SLICE_X42Y29.BY      net (fanout=91)       2.240   custom_data_in<6>
    SLICE_X42Y29.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<3>
                                                       AGNUS1/bl1/bltafwm_6
    -------------------------------------------------  ---------------------------
    Total                                     11.674ns (3.338ns logic, 8.336ns route)
                                                       (28.6% logic, 71.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_6 (SLICE_X36Y29.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.557ns (requirement - data path)
  Source:               cpu_data<6> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_6 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.443ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<6> to AGNUS1/bl1/bltalwm_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P161.I               Tiopi                 1.918   cpu_data<6>
                                                       cpu_data<6>
                                                       cpu_data_6_IOBUF/IBUF
    SLICE_X34Y17.F2      net (fanout=19)       5.189   N955
    SLICE_X34Y17.X       Tilo                  0.608   MIA1/spi_rx_data<0>
                                                       gary_cpu_data_in<6>1
    SLICE_X27Y17.F3      net (fanout=4)        0.907   gary_cpu_data_in<6>
    SLICE_X27Y17.X       Tilo                  0.551   AGNUS1/bl1/bltadat<6>
                                                       GARY1/custom_data_in<6>1
    SLICE_X36Y29.BX      net (fanout=91)       2.067   custom_data_in<6>
    SLICE_X36Y29.CLK     Tdick                 0.203   AGNUS1/bl1/bltalwm<6>
                                                       AGNUS1/bl1/bltalwm_6
    -------------------------------------------------  ---------------------------
    Total                                     11.443ns (3.280ns logic, 8.163ns route)
                                                       (28.7% logic, 71.3% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_14 (SLICE_X49Y31.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.765ns (requirement - data path)
  Source:               cpu_data<14> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_14 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.235ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<14> to AGNUS1/bl1/bltafwm_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P137.I               Tiopi                 1.918   cpu_data<14>
                                                       cpu_data<14>
                                                       cpu_data_14_IOBUF/IBUF
    SLICE_X34Y16.F1      net (fanout=22)       2.572   N947
    SLICE_X34Y16.X       Tilo                  0.608   _l_data_15
                                                       gary_cpu_data_in<14>1
    SLICE_X22Y16.F3      net (fanout=4)        1.171   gary_cpu_data_in<14>
    SLICE_X22Y16.X       Tilo                  0.608   AGNUS1/bl1/height<14>
                                                       GARY1/custom_data_in<14>1
    SLICE_X49Y31.BX      net (fanout=69)       4.155   custom_data_in<14>
    SLICE_X49Y31.CLK     Tdick                 0.203   AGNUS1/bl1/bltafwm<14>
                                                       AGNUS1/bl1/bltafwm_14
    -------------------------------------------------  ---------------------------
    Total                                     11.235ns (3.337ns logic, 7.898ns route)
                                                       (29.7% logic, 70.3% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_4 (SLICE_X43Y25.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  988.817ns (requirement - data path)
  Source:               cpu_data<4> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_4 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      11.183ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<4> to AGNUS1/bl1/bltalwm_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P166.I               Tiopi                 1.918   cpu_data<4>
                                                       cpu_data<4>
                                                       cpu_data_4_IOBUF/IBUF
    SLICE_X36Y16.F2      net (fanout=19)       3.099   N957
    SLICE_X36Y16.X       Tilo                  0.608   AGNUS1/cp1/ir2<11>
                                                       gary_cpu_data_in<4>1
    SLICE_X29Y19.G1      net (fanout=6)        2.463   gary_cpu_data_in<4>
    SLICE_X29Y19.Y       Tilo                  0.551   AGNUS1/bl1/bltadat<4>
                                                       GARY1/custom_data_in<4>1
    SLICE_X43Y25.BY      net (fanout=93)       2.283   custom_data_in<4>
    SLICE_X43Y25.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<1>
                                                       AGNUS1/bl1/bltalwm_4
    -------------------------------------------------  ---------------------------
    Total                                     11.183ns (3.338ns logic, 7.845ns route)
                                                       (29.8% logic, 70.2% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_4 (SLICE_X45Y24.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  989.441ns (requirement - data path)
  Source:               cpu_data<4> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_4 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      10.559ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<4> to AGNUS1/bl1/bltafwm_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P166.I               Tiopi                 1.918   cpu_data<4>
                                                       cpu_data<4>
                                                       cpu_data_4_IOBUF/IBUF
    SLICE_X36Y16.F2      net (fanout=19)       3.099   N957
    SLICE_X36Y16.X       Tilo                  0.608   AGNUS1/cp1/ir2<11>
                                                       gary_cpu_data_in<4>1
    SLICE_X29Y19.G1      net (fanout=6)        2.463   gary_cpu_data_in<4>
    SLICE_X29Y19.Y       Tilo                  0.551   AGNUS1/bl1/bltadat<4>
                                                       GARY1/custom_data_in<4>1
    SLICE_X45Y24.BX      net (fanout=93)       1.717   custom_data_in<4>
    SLICE_X45Y24.CLK     Tdick                 0.203   AGNUS1/bl1/bltafwm<4>
                                                       AGNUS1/bl1/bltafwm_4
    -------------------------------------------------  ---------------------------
    Total                                     10.559ns (3.280ns logic, 7.279ns route)
                                                       (31.1% logic, 68.9% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_14 (SLICE_X44Y32.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  989.571ns (requirement - data path)
  Source:               cpu_data<14> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_14 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      10.429ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<14> to AGNUS1/bl1/bltalwm_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P137.I               Tiopi                 1.918   cpu_data<14>
                                                       cpu_data<14>
                                                       cpu_data_14_IOBUF/IBUF
    SLICE_X34Y16.F1      net (fanout=22)       2.572   N947
    SLICE_X34Y16.X       Tilo                  0.608   _l_data_15
                                                       gary_cpu_data_in<14>1
    SLICE_X22Y16.F3      net (fanout=4)        1.171   gary_cpu_data_in<14>
    SLICE_X22Y16.X       Tilo                  0.608   AGNUS1/bl1/height<14>
                                                       GARY1/custom_data_in<14>1
    SLICE_X44Y32.BY      net (fanout=69)       3.291   custom_data_in<14>
    SLICE_X44Y32.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<14>
                                                       AGNUS1/bl1/bltalwm_14
    -------------------------------------------------  ---------------------------
    Total                                     10.429ns (3.395ns logic, 7.034ns route)
                                                       (32.6% logic, 67.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_0 (SLICE_X44Y29.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  989.756ns (requirement - data path)
  Source:               cpu_data<0> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_0 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      10.244ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<0> to AGNUS1/bl1/bltafwm_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P150.I               Tiopi                 1.918   cpu_data<0>
                                                       cpu_data<0>
                                                       cpu_data_0_IOBUF/IBUF
    SLICE_X35Y19.F2      net (fanout=21)       3.053   N961
    SLICE_X35Y19.X       Tilo                  0.551   _l_data_0
                                                       gary_cpu_data_in<0>1
    SLICE_X28Y19.G2      net (fanout=3)        0.980   gary_cpu_data_in<0>
    SLICE_X28Y19.Y       Tilo                  0.608   AGNUS1/bl1/bltadat<0>
                                                       GARY1/custom_data_in<0>2
    SLICE_X44Y29.BX      net (fanout=92)       2.931   custom_data_in<0>
    SLICE_X44Y29.CLK     Tdick                 0.203   AGNUS1/bl1/bltafwm<0>
                                                       AGNUS1/bl1/bltafwm_0
    -------------------------------------------------  ---------------------------
    Total                                     10.244ns (3.280ns logic, 6.964ns route)
                                                       (32.0% logic, 68.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_0 (SLICE_X45Y25.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  990.048ns (requirement - data path)
  Source:               cpu_data<0> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_0 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      9.952ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<0> to AGNUS1/bl1/bltalwm_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P150.I               Tiopi                 1.918   cpu_data<0>
                                                       cpu_data<0>
                                                       cpu_data_0_IOBUF/IBUF
    SLICE_X35Y19.F2      net (fanout=21)       3.053   N961
    SLICE_X35Y19.X       Tilo                  0.551   _l_data_0
                                                       gary_cpu_data_in<0>1
    SLICE_X28Y19.G2      net (fanout=3)        0.980   gary_cpu_data_in<0>
    SLICE_X28Y19.Y       Tilo                  0.608   AGNUS1/bl1/bltadat<0>
                                                       GARY1/custom_data_in<0>2
    SLICE_X45Y25.BY      net (fanout=92)       2.581   custom_data_in<0>
    SLICE_X45Y25.CLK     Tdick                 0.261   AGNUS1/bl1/bltalwm<0>
                                                       AGNUS1/bl1/bltalwm_0
    -------------------------------------------------  ---------------------------
    Total                                      9.952ns (3.338ns logic, 6.614ns route)
                                                       (33.5% logic, 66.5% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_1 (SLICE_X44Y29.BY), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  990.534ns (requirement - data path)
  Source:               cpu_data<1> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_1 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      9.466ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<1> to AGNUS1/bl1/bltafwm_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P154.I               Tiopi                 1.918   cpu_data<1>
                                                       cpu_data<1>
                                                       cpu_data_1_IOBUF/IBUF
    SLICE_X34Y18.F3      net (fanout=21)       3.772   N960
    SLICE_X34Y18.X       Tilo                  0.608   AGNUS1/cp1/beam_match_wait
                                                       gary_cpu_data_in<1>1
    SLICE_X36Y17.G1      net (fanout=5)        0.608   gary_cpu_data_in<1>
    SLICE_X36Y17.Y       Tilo                  0.608   AGNUS1/bl1/bltadat<1>
                                                       GARY1/custom_data_in<1>1
    SLICE_X44Y29.BY      net (fanout=96)       1.691   custom_data_in<1>
    SLICE_X44Y29.CLK     Tdick                 0.261   AGNUS1/bl1/bltafwm<0>
                                                       AGNUS1/bl1/bltafwm_1
    -------------------------------------------------  ---------------------------
    Total                                      9.466ns (3.395ns logic, 6.071ns route)
                                                       (35.9% logic, 64.1% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_1 (SLICE_X43Y25.BX), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  990.560ns (requirement - data path)
  Source:               cpu_data<1> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_1 (FF)
  Requirement:          1000.000ns
  Data Path Delay:      9.440ns (Levels of Logic = 3)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: cpu_data<1> to AGNUS1/bl1/bltalwm_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P154.I               Tiopi                 1.918   cpu_data<1>
                                                       cpu_data<1>
                                                       cpu_data_1_IOBUF/IBUF
    SLICE_X34Y18.F3      net (fanout=21)       3.772   N960
    SLICE_X34Y18.X       Tilo                  0.608   AGNUS1/cp1/beam_match_wait
                                                       gary_cpu_data_in<1>1
    SLICE_X36Y17.G1      net (fanout=5)        0.608   gary_cpu_data_in<1>
    SLICE_X36Y17.Y       Tilo                  0.608   AGNUS1/bl1/bltadat<1>
                                                       GARY1/custom_data_in<1>1
    SLICE_X43Y25.BX      net (fanout=96)       1.723   custom_data_in<1>
    SLICE_X43Y25.CLK     Tdick                 0.203   AGNUS1/bl1/bltalwm<1>
                                                       AGNUS1/bl1/bltalwm_1
    -------------------------------------------------  ---------------------------
    Total                                      9.440ns (3.337ns logic, 6.103ns route)
                                                       (35.3% logic, 64.7% route)

--------------------------------------------------------------------------------

Fastest Paths: TS_R3_CUSTOM_DATA = MAXDELAY FROM TIMEGRP "CPU_DATA" TO TIMEGRP "R3_CUSTOM_MASKS" 1000 ns DATAPATHONLY;
--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_1 (SLICE_X44Y29.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      7.123ns (data path)
  Source:               cpu_data<1> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      7.123ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<1> to AGNUS1/bl1/bltafwm_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P154.I               Tiopi                 1.530   cpu_data<1>
                                                       cpu_data<1>
                                                       cpu_data_1_IOBUF/IBUF
    SLICE_X34Y18.F3      net (fanout=21)       3.018   N960
    SLICE_X34Y18.X       Tilo                  0.486   AGNUS1/cp1/beam_match_wait
                                                       gary_cpu_data_in<1>1
    SLICE_X36Y17.G1      net (fanout=5)        0.487   gary_cpu_data_in<1>
    SLICE_X36Y17.Y       Tilo                  0.486   AGNUS1/bl1/bltadat<1>
                                                       GARY1/custom_data_in<1>1
    SLICE_X44Y29.BY      net (fanout=96)       1.353   custom_data_in<1>
    SLICE_X44Y29.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<0>
                                                       AGNUS1/bl1/bltafwm_1
    -------------------------------------------------  ---------------------------
    Total                                      7.123ns (2.265ns logic, 4.858ns route)
                                                       (31.8% logic, 68.2% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_1 (SLICE_X43Y25.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      7.102ns (data path)
  Source:               cpu_data<1> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      7.102ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<1> to AGNUS1/bl1/bltalwm_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P154.I               Tiopi                 1.530   cpu_data<1>
                                                       cpu_data<1>
                                                       cpu_data_1_IOBUF/IBUF
    SLICE_X34Y18.F3      net (fanout=21)       3.018   N960
    SLICE_X34Y18.X       Tilo                  0.486   AGNUS1/cp1/beam_match_wait
                                                       gary_cpu_data_in<1>1
    SLICE_X36Y17.G1      net (fanout=5)        0.487   gary_cpu_data_in<1>
    SLICE_X36Y17.Y       Tilo                  0.486   AGNUS1/bl1/bltadat<1>
                                                       GARY1/custom_data_in<1>1
    SLICE_X43Y25.BX      net (fanout=96)       1.378   custom_data_in<1>
    SLICE_X43Y25.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltalwm<1>
                                                       AGNUS1/bl1/bltalwm_1
    -------------------------------------------------  ---------------------------
    Total                                      7.102ns (2.219ns logic, 4.883ns route)
                                                       (31.2% logic, 68.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_0 (SLICE_X45Y25.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      7.512ns (data path)
  Source:               cpu_data<0> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      7.512ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<0> to AGNUS1/bl1/bltalwm_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P150.I               Tiopi                 1.530   cpu_data<0>
                                                       cpu_data<0>
                                                       cpu_data_0_IOBUF/IBUF
    SLICE_X35Y19.F2      net (fanout=21)       2.443   N961
    SLICE_X35Y19.X       Tilo                  0.441   _l_data_0
                                                       gary_cpu_data_in<0>1
    SLICE_X28Y19.G2      net (fanout=3)        0.784   gary_cpu_data_in<0>
    SLICE_X28Y19.Y       Tilo                  0.486   AGNUS1/bl1/bltadat<0>
                                                       GARY1/custom_data_in<0>2
    SLICE_X45Y25.BY      net (fanout=92)       2.065   custom_data_in<0>
    SLICE_X45Y25.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<0>
                                                       AGNUS1/bl1/bltalwm_0
    -------------------------------------------------  ---------------------------
    Total                                      7.512ns (2.220ns logic, 5.292ns route)
                                                       (29.6% logic, 70.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_0 (SLICE_X44Y29.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      7.746ns (data path)
  Source:               cpu_data<0> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      7.746ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<0> to AGNUS1/bl1/bltafwm_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P150.I               Tiopi                 1.530   cpu_data<0>
                                                       cpu_data<0>
                                                       cpu_data_0_IOBUF/IBUF
    SLICE_X35Y19.F2      net (fanout=21)       2.443   N961
    SLICE_X35Y19.X       Tilo                  0.441   _l_data_0
                                                       gary_cpu_data_in<0>1
    SLICE_X28Y19.G2      net (fanout=3)        0.784   gary_cpu_data_in<0>
    SLICE_X28Y19.Y       Tilo                  0.486   AGNUS1/bl1/bltadat<0>
                                                       GARY1/custom_data_in<0>2
    SLICE_X44Y29.BX      net (fanout=92)       2.345   custom_data_in<0>
    SLICE_X44Y29.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltafwm<0>
                                                       AGNUS1/bl1/bltafwm_0
    -------------------------------------------------  ---------------------------
    Total                                      7.746ns (2.174ns logic, 5.572ns route)
                                                       (28.1% logic, 71.9% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_14 (SLICE_X44Y32.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      7.892ns (data path)
  Source:               cpu_data<14> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_14 (FF)
  Requirement:          0.000ns
  Data Path Delay:      7.892ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<14> to AGNUS1/bl1/bltalwm_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P137.I               Tiopi                 1.530   cpu_data<14>
                                                       cpu_data<14>
                                                       cpu_data_14_IOBUF/IBUF
    SLICE_X34Y16.F1      net (fanout=22)       2.057   N947
    SLICE_X34Y16.X       Tilo                  0.486   _l_data_15
                                                       gary_cpu_data_in<14>1
    SLICE_X22Y16.F3      net (fanout=4)        0.937   gary_cpu_data_in<14>
    SLICE_X22Y16.X       Tilo                  0.486   AGNUS1/bl1/height<14>
                                                       GARY1/custom_data_in<14>1
    SLICE_X44Y32.BY      net (fanout=69)       2.633   custom_data_in<14>
    SLICE_X44Y32.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<14>
                                                       AGNUS1/bl1/bltalwm_14
    -------------------------------------------------  ---------------------------
    Total                                      7.892ns (2.265ns logic, 5.627ns route)
                                                       (28.7% logic, 71.3% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_4 (SLICE_X45Y24.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      7.997ns (data path)
  Source:               cpu_data<4> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      7.997ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<4> to AGNUS1/bl1/bltafwm_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P166.I               Tiopi                 1.530   cpu_data<4>
                                                       cpu_data<4>
                                                       cpu_data_4_IOBUF/IBUF
    SLICE_X36Y16.F2      net (fanout=19)       2.479   N957
    SLICE_X36Y16.X       Tilo                  0.486   AGNUS1/cp1/ir2<11>
                                                       gary_cpu_data_in<4>1
    SLICE_X29Y19.G1      net (fanout=6)        1.970   gary_cpu_data_in<4>
    SLICE_X29Y19.Y       Tilo                  0.441   AGNUS1/bl1/bltadat<4>
                                                       GARY1/custom_data_in<4>1
    SLICE_X45Y24.BX      net (fanout=93)       1.374   custom_data_in<4>
    SLICE_X45Y24.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltafwm<4>
                                                       AGNUS1/bl1/bltafwm_4
    -------------------------------------------------  ---------------------------
    Total                                      7.997ns (2.174ns logic, 5.823ns route)
                                                       (27.2% logic, 72.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_4 (SLICE_X43Y25.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.495ns (data path)
  Source:               cpu_data<4> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.495ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<4> to AGNUS1/bl1/bltalwm_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P166.I               Tiopi                 1.530   cpu_data<4>
                                                       cpu_data<4>
                                                       cpu_data_4_IOBUF/IBUF
    SLICE_X36Y16.F2      net (fanout=19)       2.479   N957
    SLICE_X36Y16.X       Tilo                  0.486   AGNUS1/cp1/ir2<11>
                                                       gary_cpu_data_in<4>1
    SLICE_X29Y19.G1      net (fanout=6)        1.970   gary_cpu_data_in<4>
    SLICE_X29Y19.Y       Tilo                  0.441   AGNUS1/bl1/bltadat<4>
                                                       GARY1/custom_data_in<4>1
    SLICE_X43Y25.BY      net (fanout=93)       1.826   custom_data_in<4>
    SLICE_X43Y25.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<1>
                                                       AGNUS1/bl1/bltalwm_4
    -------------------------------------------------  ---------------------------
    Total                                      8.495ns (2.220ns logic, 6.275ns route)
                                                       (26.1% logic, 73.9% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_14 (SLICE_X49Y31.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.537ns (data path)
  Source:               cpu_data<14> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_14 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.537ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<14> to AGNUS1/bl1/bltafwm_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P137.I               Tiopi                 1.530   cpu_data<14>
                                                       cpu_data<14>
                                                       cpu_data_14_IOBUF/IBUF
    SLICE_X34Y16.F1      net (fanout=22)       2.057   N947
    SLICE_X34Y16.X       Tilo                  0.486   _l_data_15
                                                       gary_cpu_data_in<14>1
    SLICE_X22Y16.F3      net (fanout=4)        0.937   gary_cpu_data_in<14>
    SLICE_X22Y16.X       Tilo                  0.486   AGNUS1/bl1/height<14>
                                                       GARY1/custom_data_in<14>1
    SLICE_X49Y31.BX      net (fanout=69)       3.324   custom_data_in<14>
    SLICE_X49Y31.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltafwm<14>
                                                       AGNUS1/bl1/bltafwm_14
    -------------------------------------------------  ---------------------------
    Total                                      8.537ns (2.219ns logic, 6.318ns route)
                                                       (26.0% logic, 74.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_6 (SLICE_X36Y29.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.705ns (data path)
  Source:               cpu_data<6> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.705ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<6> to AGNUS1/bl1/bltalwm_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P161.I               Tiopi                 1.530   cpu_data<6>
                                                       cpu_data<6>
                                                       cpu_data_6_IOBUF/IBUF
    SLICE_X34Y17.F2      net (fanout=19)       4.151   N955
    SLICE_X34Y17.X       Tilo                  0.486   MIA1/spi_rx_data<0>
                                                       gary_cpu_data_in<6>1
    SLICE_X27Y17.F3      net (fanout=4)        0.726   gary_cpu_data_in<6>
    SLICE_X27Y17.X       Tilo                  0.441   AGNUS1/bl1/bltadat<6>
                                                       GARY1/custom_data_in<6>1
    SLICE_X36Y29.BX      net (fanout=91)       1.654   custom_data_in<6>
    SLICE_X36Y29.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltalwm<6>
                                                       AGNUS1/bl1/bltalwm_6
    -------------------------------------------------  ---------------------------
    Total                                      8.705ns (2.174ns logic, 6.531ns route)
                                                       (25.0% logic, 75.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_6 (SLICE_X42Y29.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      8.889ns (data path)
  Source:               cpu_data<6> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      8.889ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<6> to AGNUS1/bl1/bltafwm_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P161.I               Tiopi                 1.530   cpu_data<6>
                                                       cpu_data<6>
                                                       cpu_data_6_IOBUF/IBUF
    SLICE_X34Y17.F2      net (fanout=19)       4.151   N955
    SLICE_X34Y17.X       Tilo                  0.486   MIA1/spi_rx_data<0>
                                                       gary_cpu_data_in<6>1
    SLICE_X27Y17.F3      net (fanout=4)        0.726   gary_cpu_data_in<6>
    SLICE_X27Y17.X       Tilo                  0.441   AGNUS1/bl1/bltadat<6>
                                                       GARY1/custom_data_in<6>1
    SLICE_X42Y29.BY      net (fanout=91)       1.792   custom_data_in<6>
    SLICE_X42Y29.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<3>
                                                       AGNUS1/bl1/bltafwm_6
    -------------------------------------------------  ---------------------------
    Total                                      8.889ns (2.220ns logic, 6.669ns route)
                                                       (25.0% logic, 75.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_2 (SLICE_X43Y26.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.074ns (data path)
  Source:               cpu_data<2> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.074ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<2> to AGNUS1/bl1/bltafwm_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P156.I               Tiopi                 1.530   cpu_data<2>
                                                       cpu_data<2>
                                                       cpu_data_2_IOBUF/IBUF
    SLICE_X24Y23.F3      net (fanout=20)       4.349   N959
    SLICE_X24Y23.X       Tilo                  0.486   gary_cpu_data_in<2>
                                                       gary_cpu_data_in<2>1
    SLICE_X24Y27.F1      net (fanout=3)        0.746   gary_cpu_data_in<2>
    SLICE_X24Y27.X       Tilo                  0.486   AGNUS1/bl1/bltadat<2>
                                                       GARY1/custom_data_in<2>1
    SLICE_X43Y26.BY      net (fanout=99)       1.714   custom_data_in<2>
    SLICE_X43Y26.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<2>
                                                       AGNUS1/bl1/bltafwm_2
    -------------------------------------------------  ---------------------------
    Total                                      9.074ns (2.265ns logic, 6.809ns route)
                                                       (25.0% logic, 75.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_7 (SLICE_X36Y29.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.083ns (data path)
  Source:               cpu_data<7> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.083ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<7> to AGNUS1/bl1/bltalwm_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P155.I               Tiopi                 1.530   cpu_data<7>
                                                       cpu_data<7>
                                                       cpu_data_7_IOBUF/IBUF
    SLICE_X29Y16.G3      net (fanout=22)       4.336   N954
    SLICE_X29Y16.Y       Tilo                  0.441   gary_cpu_data_in<15>
                                                       gary_cpu_data_in<7>1
    SLICE_X30Y21.F2      net (fanout=5)        0.983   gary_cpu_data_in<7>
    SLICE_X30Y21.X       Tilo                  0.486   AGNUS1/bl1/bltadat<7>
                                                       GARY1/custom_data_in<7>1
    SLICE_X36Y29.BY      net (fanout=84)       1.544   custom_data_in<7>
    SLICE_X36Y29.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<6>
                                                       AGNUS1/bl1/bltalwm_7
    -------------------------------------------------  ---------------------------
    Total                                      9.083ns (2.220ns logic, 6.863ns route)
                                                       (24.4% logic, 75.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_7 (SLICE_X41Y27.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.085ns (data path)
  Source:               cpu_data<7> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.085ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<7> to AGNUS1/bl1/bltafwm_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P155.I               Tiopi                 1.530   cpu_data<7>
                                                       cpu_data<7>
                                                       cpu_data_7_IOBUF/IBUF
    SLICE_X29Y16.G3      net (fanout=22)       4.336   N954
    SLICE_X29Y16.Y       Tilo                  0.441   gary_cpu_data_in<15>
                                                       gary_cpu_data_in<7>1
    SLICE_X30Y21.F2      net (fanout=5)        0.983   gary_cpu_data_in<7>
    SLICE_X30Y21.X       Tilo                  0.486   AGNUS1/bl1/bltadat<7>
                                                       GARY1/custom_data_in<7>1
    SLICE_X41Y27.BY      net (fanout=84)       1.546   custom_data_in<7>
    SLICE_X41Y27.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<7>
                                                       AGNUS1/bl1/bltafwm_7
    -------------------------------------------------  ---------------------------
    Total                                      9.085ns (2.220ns logic, 6.865ns route)
                                                       (24.4% logic, 75.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_15 (SLICE_X49Y31.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.103ns (data path)
  Source:               cpu_data<15> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_15 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.103ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<15> to AGNUS1/bl1/bltafwm_15
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P135.I               Tiopi                 1.530   cpu_data<15>
                                                       cpu_data<15>
                                                       cpu_data_15_IOBUF/IBUF
    SLICE_X29Y16.F2      net (fanout=27)       3.359   N946
    SLICE_X29Y16.X       Tilo                  0.441   gary_cpu_data_in<15>
                                                       gary_cpu_data_in<15>1
    SLICE_X20Y22.F3      net (fanout=5)        1.061   gary_cpu_data_in<15>
    SLICE_X20Y22.X       Tilo                  0.486   AGNUS1/bpd1/vdiwstop<7>
                                                       GARY1/custom_data_in<15>1
    SLICE_X49Y31.BY      net (fanout=131)      2.463   custom_data_in<15>
    SLICE_X49Y31.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<14>
                                                       AGNUS1/bl1/bltafwm_15
    -------------------------------------------------  ---------------------------
    Total                                      9.103ns (2.220ns logic, 6.883ns route)
                                                       (24.4% logic, 75.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_3 (SLICE_X45Y26.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.196ns (data path)
  Source:               cpu_data<3> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.196ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<3> to AGNUS1/bl1/bltalwm_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P162.I               Tiopi                 1.530   cpu_data<3>
                                                       cpu_data<3>
                                                       cpu_data_3_IOBUF/IBUF
    SLICE_X36Y21.F2      net (fanout=20)       4.152   N958
    SLICE_X36Y21.X       Tilo                  0.486   _l_data_3
                                                       gary_cpu_data_in<3>1
    SLICE_X30Y25.G1      net (fanout=5)        1.514   gary_cpu_data_in<3>
    SLICE_X30Y25.Y       Tilo                  0.486   AGNUS1/bl1/bltadat<3>
                                                       GARY1/custom_data_in<3>1
    SLICE_X45Y26.BY      net (fanout=93)       1.265   custom_data_in<3>
    SLICE_X45Y26.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<2>
                                                       AGNUS1/bl1/bltalwm_3
    -------------------------------------------------  ---------------------------
    Total                                      9.196ns (2.265ns logic, 6.931ns route)
                                                       (24.6% logic, 75.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_2 (SLICE_X45Y26.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.190ns (data path)
  Source:               cpu_data<2> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.190ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<2> to AGNUS1/bl1/bltalwm_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P156.I               Tiopi                 1.530   cpu_data<2>
                                                       cpu_data<2>
                                                       cpu_data_2_IOBUF/IBUF
    SLICE_X24Y23.F3      net (fanout=20)       4.349   N959
    SLICE_X24Y23.X       Tilo                  0.486   gary_cpu_data_in<2>
                                                       gary_cpu_data_in<2>1
    SLICE_X24Y27.F1      net (fanout=3)        0.746   gary_cpu_data_in<2>
    SLICE_X24Y27.X       Tilo                  0.486   AGNUS1/bl1/bltadat<2>
                                                       GARY1/custom_data_in<2>1
    SLICE_X45Y26.BX      net (fanout=99)       1.876   custom_data_in<2>
    SLICE_X45Y26.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltalwm<2>
                                                       AGNUS1/bl1/bltalwm_2
    -------------------------------------------------  ---------------------------
    Total                                      9.190ns (2.219ns logic, 6.971ns route)
                                                       (24.1% logic, 75.9% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_15 (SLICE_X49Y33.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.386ns (data path)
  Source:               cpu_data<15> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_15 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.386ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<15> to AGNUS1/bl1/bltalwm_15
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P135.I               Tiopi                 1.530   cpu_data<15>
                                                       cpu_data<15>
                                                       cpu_data_15_IOBUF/IBUF
    SLICE_X29Y16.F2      net (fanout=27)       3.359   N946
    SLICE_X29Y16.X       Tilo                  0.441   gary_cpu_data_in<15>
                                                       gary_cpu_data_in<15>1
    SLICE_X20Y22.F3      net (fanout=5)        1.061   gary_cpu_data_in<15>
    SLICE_X20Y22.X       Tilo                  0.486   AGNUS1/bpd1/vdiwstop<7>
                                                       GARY1/custom_data_in<15>1
    SLICE_X49Y33.BY      net (fanout=131)      2.746   custom_data_in<15>
    SLICE_X49Y33.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<15>
                                                       AGNUS1/bl1/bltalwm_15
    -------------------------------------------------  ---------------------------
    Total                                      9.386ns (2.220ns logic, 7.166ns route)
                                                       (23.7% logic, 76.3% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_3 (SLICE_X42Y29.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.517ns (data path)
  Source:               cpu_data<3> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.517ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<3> to AGNUS1/bl1/bltafwm_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P162.I               Tiopi                 1.530   cpu_data<3>
                                                       cpu_data<3>
                                                       cpu_data_3_IOBUF/IBUF
    SLICE_X36Y21.F2      net (fanout=20)       4.152   N958
    SLICE_X36Y21.X       Tilo                  0.486   _l_data_3
                                                       gary_cpu_data_in<3>1
    SLICE_X30Y25.G1      net (fanout=5)        1.514   gary_cpu_data_in<3>
    SLICE_X30Y25.Y       Tilo                  0.486   AGNUS1/bl1/bltadat<3>
                                                       GARY1/custom_data_in<3>1
    SLICE_X42Y29.BX      net (fanout=93)       1.632   custom_data_in<3>
    SLICE_X42Y29.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltafwm<3>
                                                       AGNUS1/bl1/bltafwm_3
    -------------------------------------------------  ---------------------------
    Total                                      9.517ns (2.219ns logic, 7.298ns route)
                                                       (23.3% logic, 76.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_5 (SLICE_X45Y24.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.861ns (data path)
  Source:               cpu_data<5> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_5 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.861ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<5> to AGNUS1/bl1/bltafwm_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P165.I               Tiopi                 1.530   cpu_data<5>
                                                       cpu_data<5>
                                                       cpu_data_5_IOBUF/IBUF
    SLICE_X36Y16.G2      net (fanout=19)       3.130   N956
    SLICE_X36Y16.Y       Tilo                  0.486   AGNUS1/cp1/ir2<11>
                                                       gary_cpu_data_in<5>1
    SLICE_X28Y16.F3      net (fanout=4)        1.725   gary_cpu_data_in<5>
    SLICE_X28Y16.X       Tilo                  0.486   AGNUS1/bl1/bltadat<5>
                                                       GARY1/custom_data_in<5>1
    SLICE_X45Y24.BY      net (fanout=89)       2.741   custom_data_in<5>
    SLICE_X45Y24.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<4>
                                                       AGNUS1/bl1/bltafwm_5
    -------------------------------------------------  ---------------------------
    Total                                      9.861ns (2.265ns logic, 7.596ns route)
                                                       (23.0% logic, 77.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_9 (SLICE_X44Y28.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      9.931ns (data path)
  Source:               cpu_data<9> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_9 (FF)
  Requirement:          0.000ns
  Data Path Delay:      9.931ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<9> to AGNUS1/bl1/bltalwm_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P149.I               Tiopi                 1.530   cpu_data<9>
                                                       cpu_data<9>
                                                       cpu_data_9_IOBUF/IBUF
    SLICE_X26Y14.F4      net (fanout=22)       3.735   N952
    SLICE_X26Y14.X       Tilo                  0.486   DENISE1/sprm0/sps2/datlb<10>
                                                       gary_cpu_data_in<9>1
    SLICE_X27Y21.F1      net (fanout=3)        2.287   gary_cpu_data_in<9>
    SLICE_X27Y21.X       Tilo                  0.441   AGNUS1/bl1/bltadat<9>
                                                       GARY1/custom_data_in<9>1
    SLICE_X44Y28.BY      net (fanout=73)       1.689   custom_data_in<9>
    SLICE_X44Y28.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<5>
                                                       AGNUS1/bl1/bltalwm_9
    -------------------------------------------------  ---------------------------
    Total                                      9.931ns (2.220ns logic, 7.711ns route)
                                                       (22.4% logic, 77.6% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_5 (SLICE_X44Y28.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      10.103ns (data path)
  Source:               cpu_data<5> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_5 (FF)
  Requirement:          0.000ns
  Data Path Delay:      10.103ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<5> to AGNUS1/bl1/bltalwm_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P165.I               Tiopi                 1.530   cpu_data<5>
                                                       cpu_data<5>
                                                       cpu_data_5_IOBUF/IBUF
    SLICE_X36Y16.G2      net (fanout=19)       3.130   N956
    SLICE_X36Y16.Y       Tilo                  0.486   AGNUS1/cp1/ir2<11>
                                                       gary_cpu_data_in<5>1
    SLICE_X28Y16.F3      net (fanout=4)        1.725   gary_cpu_data_in<5>
    SLICE_X28Y16.X       Tilo                  0.486   AGNUS1/bl1/bltadat<5>
                                                       GARY1/custom_data_in<5>1
    SLICE_X44Y28.BX      net (fanout=89)       3.029   custom_data_in<5>
    SLICE_X44Y28.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltalwm<5>
                                                       AGNUS1/bl1/bltalwm_5
    -------------------------------------------------  ---------------------------
    Total                                     10.103ns (2.219ns logic, 7.884ns route)
                                                       (22.0% logic, 78.0% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_9 (SLICE_X47Y31.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      10.212ns (data path)
  Source:               cpu_data<9> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_9 (FF)
  Requirement:          0.000ns
  Data Path Delay:      10.212ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<9> to AGNUS1/bl1/bltafwm_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P149.I               Tiopi                 1.530   cpu_data<9>
                                                       cpu_data<9>
                                                       cpu_data_9_IOBUF/IBUF
    SLICE_X26Y14.F4      net (fanout=22)       3.735   N952
    SLICE_X26Y14.X       Tilo                  0.486   DENISE1/sprm0/sps2/datlb<10>
                                                       gary_cpu_data_in<9>1
    SLICE_X27Y21.F1      net (fanout=3)        2.287   gary_cpu_data_in<9>
    SLICE_X27Y21.X       Tilo                  0.441   AGNUS1/bl1/bltadat<9>
                                                       GARY1/custom_data_in<9>1
    SLICE_X47Y31.BY      net (fanout=73)       1.970   custom_data_in<9>
    SLICE_X47Y31.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<8>
                                                       AGNUS1/bl1/bltafwm_9
    -------------------------------------------------  ---------------------------
    Total                                     10.212ns (2.220ns logic, 7.992ns route)
                                                       (21.7% logic, 78.3% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_13 (SLICE_X45Y30.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      10.228ns (data path)
  Source:               cpu_data<13> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_13 (FF)
  Requirement:          0.000ns
  Data Path Delay:      10.228ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<13> to AGNUS1/bl1/bltalwm_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P139.I               Tiopi                 1.530   cpu_data<13>
                                                       cpu_data<13>
                                                       cpu_data_13_IOBUF/IBUF
    SLICE_X23Y19.F1      net (fanout=21)       3.938   N948
    SLICE_X23Y19.X       Tilo                  0.441   DENISE1/sprm0/sps0/datlb<13>
                                                       gary_cpu_data_in<13>1
    SLICE_X18Y16.F3      net (fanout=4)        1.235   gary_cpu_data_in<13>
    SLICE_X18Y16.X       Tilo                  0.486   AGNUS1/bl1/height<13>
                                                       GARY1/custom_data_in<13>1
    SLICE_X45Y30.BY      net (fanout=70)       2.835   custom_data_in<13>
    SLICE_X45Y30.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<12>
                                                       AGNUS1/bl1/bltalwm_13
    -------------------------------------------------  ---------------------------
    Total                                     10.228ns (2.220ns logic, 8.008ns route)
                                                       (21.7% logic, 78.3% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_10 (SLICE_X48Y32.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      10.215ns (data path)
  Source:               cpu_data<10> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_10 (FF)
  Requirement:          0.000ns
  Data Path Delay:      10.215ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<10> to AGNUS1/bl1/bltafwm_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P147.I               Tiopi                 1.530   cpu_data<10>
                                                       cpu_data<10>
                                                       cpu_data_10_IOBUF/IBUF
    SLICE_X24Y15.F3      net (fanout=22)       3.567   N951
    SLICE_X24Y15.X       Tilo                  0.486   _l_data_12
                                                       gary_cpu_data_in<10>1
    SLICE_X17Y15.F1      net (fanout=3)        1.858   gary_cpu_data_in<10>
    SLICE_X17Y15.X       Tilo                  0.441   AGNUS1/bl1/height<10>
                                                       GARY1/custom_data_in<10>1
    SLICE_X48Y32.BX      net (fanout=75)       2.616   custom_data_in<10>
    SLICE_X48Y32.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltafwm<10>
                                                       AGNUS1/bl1/bltafwm_10
    -------------------------------------------------  ---------------------------
    Total                                     10.215ns (2.174ns logic, 8.041ns route)
                                                       (21.3% logic, 78.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_10 (SLICE_X46Y28.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      10.293ns (data path)
  Source:               cpu_data<10> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_10 (FF)
  Requirement:          0.000ns
  Data Path Delay:      10.293ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<10> to AGNUS1/bl1/bltalwm_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P147.I               Tiopi                 1.530   cpu_data<10>
                                                       cpu_data<10>
                                                       cpu_data_10_IOBUF/IBUF
    SLICE_X24Y15.F3      net (fanout=22)       3.567   N951
    SLICE_X24Y15.X       Tilo                  0.486   _l_data_12
                                                       gary_cpu_data_in<10>1
    SLICE_X17Y15.F1      net (fanout=3)        1.858   gary_cpu_data_in<10>
    SLICE_X17Y15.X       Tilo                  0.441   AGNUS1/bl1/height<10>
                                                       GARY1/custom_data_in<10>1
    SLICE_X46Y28.BX      net (fanout=75)       2.694   custom_data_in<10>
    SLICE_X46Y28.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltalwm<10>
                                                       AGNUS1/bl1/bltalwm_10
    -------------------------------------------------  ---------------------------
    Total                                     10.293ns (2.174ns logic, 8.119ns route)
                                                       (21.1% logic, 78.9% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_8 (SLICE_X41Y28.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      10.560ns (data path)
  Source:               cpu_data<8> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      10.560ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<8> to AGNUS1/bl1/bltalwm_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P152.I               Tiopi                 1.530   cpu_data<8>
                                                       cpu_data<8>
                                                       cpu_data_8_IOBUF/IBUF
    SLICE_X27Y14.G1      net (fanout=22)       5.012   N953
    SLICE_X27Y14.Y       Tilo                  0.441   _l_data_11
                                                       gary_cpu_data_in<8>1
    SLICE_X29Y15.F2      net (fanout=3)        0.480   gary_cpu_data_in<8>
    SLICE_X29Y15.X       Tilo                  0.441   AGNUS1/bl1/bltadat<8>
                                                       GARY1/custom_data_in<8>1
    SLICE_X41Y28.BY      net (fanout=72)       2.893   custom_data_in<8>
    SLICE_X41Y28.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<8>
                                                       AGNUS1/bl1/bltalwm_8
    -------------------------------------------------  ---------------------------
    Total                                     10.560ns (2.175ns logic, 8.385ns route)
                                                       (20.6% logic, 79.4% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_8 (SLICE_X47Y31.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      10.537ns (data path)
  Source:               cpu_data<8> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      10.537ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<8> to AGNUS1/bl1/bltafwm_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P152.I               Tiopi                 1.530   cpu_data<8>
                                                       cpu_data<8>
                                                       cpu_data_8_IOBUF/IBUF
    SLICE_X27Y14.G1      net (fanout=22)       5.012   N953
    SLICE_X27Y14.Y       Tilo                  0.441   _l_data_11
                                                       gary_cpu_data_in<8>1
    SLICE_X29Y15.F2      net (fanout=3)        0.480   gary_cpu_data_in<8>
    SLICE_X29Y15.X       Tilo                  0.441   AGNUS1/bl1/bltadat<8>
                                                       GARY1/custom_data_in<8>1
    SLICE_X47Y31.BX      net (fanout=72)       2.916   custom_data_in<8>
    SLICE_X47Y31.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltafwm<8>
                                                       AGNUS1/bl1/bltafwm_8
    -------------------------------------------------  ---------------------------
    Total                                     10.537ns (2.129ns logic, 8.408ns route)
                                                       (20.2% logic, 79.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_11 (SLICE_X48Y32.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      10.954ns (data path)
  Source:               cpu_data<11> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_11 (FF)
  Requirement:          0.000ns
  Data Path Delay:      10.954ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<11> to AGNUS1/bl1/bltafwm_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P144.I               Tiopi                 1.530   cpu_data<11>
                                                       cpu_data<11>
                                                       cpu_data_11_IOBUF/IBUF
    SLICE_X24Y15.G1      net (fanout=21)       3.358   N950
    SLICE_X24Y15.Y       Tilo                  0.486   _l_data_12
                                                       gary_cpu_data_in<11>1
    SLICE_X17Y11.F2      net (fanout=3)        2.015   gary_cpu_data_in<11>
    SLICE_X17Y11.X       Tilo                  0.441   AGNUS1/bl1/height<11>
                                                       GARY1/custom_data_in<11>1
    SLICE_X48Y32.BY      net (fanout=72)       3.361   custom_data_in<11>
    SLICE_X48Y32.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<10>
                                                       AGNUS1/bl1/bltafwm_11
    -------------------------------------------------  ---------------------------
    Total                                     10.954ns (2.220ns logic, 8.734ns route)
                                                       (20.3% logic, 79.7% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_13 (SLICE_X48Y34.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      10.975ns (data path)
  Source:               cpu_data<13> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_13 (FF)
  Requirement:          0.000ns
  Data Path Delay:      10.975ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<13> to AGNUS1/bl1/bltafwm_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P139.I               Tiopi                 1.530   cpu_data<13>
                                                       cpu_data<13>
                                                       cpu_data_13_IOBUF/IBUF
    SLICE_X23Y19.F1      net (fanout=21)       3.938   N948
    SLICE_X23Y19.X       Tilo                  0.441   DENISE1/sprm0/sps0/datlb<13>
                                                       gary_cpu_data_in<13>1
    SLICE_X18Y16.F3      net (fanout=4)        1.235   gary_cpu_data_in<13>
    SLICE_X18Y16.X       Tilo                  0.486   AGNUS1/bl1/height<13>
                                                       GARY1/custom_data_in<13>1
    SLICE_X48Y34.BY      net (fanout=70)       3.582   custom_data_in<13>
    SLICE_X48Y34.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltafwm<12>
                                                       AGNUS1/bl1/bltafwm_13
    -------------------------------------------------  ---------------------------
    Total                                     10.975ns (2.220ns logic, 8.755ns route)
                                                       (20.2% logic, 79.8% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_11 (SLICE_X46Y28.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      11.066ns (data path)
  Source:               cpu_data<11> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_11 (FF)
  Requirement:          0.000ns
  Data Path Delay:      11.066ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<11> to AGNUS1/bl1/bltalwm_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P144.I               Tiopi                 1.530   cpu_data<11>
                                                       cpu_data<11>
                                                       cpu_data_11_IOBUF/IBUF
    SLICE_X24Y15.G1      net (fanout=21)       3.358   N950
    SLICE_X24Y15.Y       Tilo                  0.486   _l_data_12
                                                       gary_cpu_data_in<11>1
    SLICE_X17Y11.F2      net (fanout=3)        2.015   gary_cpu_data_in<11>
    SLICE_X17Y11.X       Tilo                  0.441   AGNUS1/bl1/height<11>
                                                       GARY1/custom_data_in<11>1
    SLICE_X46Y28.BY      net (fanout=72)       3.473   custom_data_in<11>
    SLICE_X46Y28.CLK     Tckdi       (-Th)     0.237   AGNUS1/bl1/bltalwm<10>
                                                       AGNUS1/bl1/bltalwm_11
    -------------------------------------------------  ---------------------------
    Total                                     11.066ns (2.220ns logic, 8.846ns route)
                                                       (20.1% logic, 79.9% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltalwm_12 (SLICE_X45Y30.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      11.156ns (data path)
  Source:               cpu_data<12> (PAD)
  Destination:          AGNUS1/bl1/bltalwm_12 (FF)
  Requirement:          0.000ns
  Data Path Delay:      11.156ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<12> to AGNUS1/bl1/bltalwm_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P141.I               Tiopi                 1.530   cpu_data<12>
                                                       cpu_data<12>
                                                       cpu_data_12_IOBUF/IBUF
    SLICE_X22Y14.F3      net (fanout=23)       4.234   N949
    SLICE_X22Y14.X       Tilo                  0.486   AGNUS1/bpd1/dmaena_delayed<0>
                                                       gary_cpu_data_in<12>1
    SLICE_X17Y19.F3      net (fanout=4)        1.199   gary_cpu_data_in<12>
    SLICE_X17Y19.X       Tilo                  0.441   AGNUS1/bl1/height<12>
                                                       GARY1/custom_data_in<12>1
    SLICE_X45Y30.BX      net (fanout=70)       3.549   custom_data_in<12>
    SLICE_X45Y30.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltalwm<12>
                                                       AGNUS1/bl1/bltalwm_12
    -------------------------------------------------  ---------------------------
    Total                                     11.156ns (2.174ns logic, 8.982ns route)
                                                       (19.5% logic, 80.5% route)

--------------------------------------------------------------------------------

Paths for end point AGNUS1/bl1/bltafwm_12 (SLICE_X48Y34.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      11.833ns (data path)
  Source:               cpu_data<12> (PAD)
  Destination:          AGNUS1/bl1/bltafwm_12 (FF)
  Requirement:          0.000ns
  Data Path Delay:      11.833ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<12> to AGNUS1/bl1/bltafwm_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P141.I               Tiopi                 1.530   cpu_data<12>
                                                       cpu_data<12>
                                                       cpu_data_12_IOBUF/IBUF
    SLICE_X22Y14.F3      net (fanout=23)       4.234   N949
    SLICE_X22Y14.X       Tilo                  0.486   AGNUS1/bpd1/dmaena_delayed<0>
                                                       gary_cpu_data_in<12>1
    SLICE_X17Y19.F3      net (fanout=4)        1.199   gary_cpu_data_in<12>
    SLICE_X17Y19.X       Tilo                  0.441   AGNUS1/bl1/height<12>
                                                       GARY1/custom_data_in<12>1
    SLICE_X48Y34.BX      net (fanout=70)       4.226   custom_data_in<12>
    SLICE_X48Y34.CLK     Tckdi       (-Th)     0.283   AGNUS1/bl1/bltafwm<12>
                                                       AGNUS1/bl1/bltafwm_12
    -------------------------------------------------  ---------------------------
    Total                                     11.833ns (2.174ns logic, 9.659ns route)
                                                       (18.4% logic, 81.6% route)

--------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_chip28
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_chip28                      |     35.242ns|     33.338ns|     32.723ns|            0|            0|      1807016|    154406524|
| TS_chip7                      |    140.968ns|    130.892ns|          N/A|            0|            0|    154406524|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.


Timing summary:
---------------

Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)

Constraints cover 156215758 paths, 0 nets, and 26347 connections

Design statistics:
   Minimum period: 130.892ns{1}   (Maximum frequency:   7.640MHz)
   Maximum path delay from/to any node:  15.354ns


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Thu Sep 17 17:19:32 2026 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 418 MB



