TS11 maximum
21.883ns (requirement - data path)
  Source:               RAM1/_ce_1 (FF)
  Destination:          _ram_ce<1> (PAD)
  Requirement:          33.000ns
  Data Path Delay:      11.117ns (Levels of Logic = 1)
  Source Clock:         clk28m rising at 0.000ns

  Maximum Data Path: RAM1/_ce_1 to _ram_ce<1>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X17Y31.YQ      Tcko                  0.720   _ce_1
                                                       RAM1/_ce_1
    P20.O1               net (fanout=1)        3.391   _ce_1
    P20.PAD              Tioop                 7.006   _ram_ce<1>
                                                       &ram_ce_1_OBUF
                                                       _ram_ce<1>
    -------------------------------------------------  ---------------------------
    Total                                     11.117ns (7.726ns logic, 3.391ns route)
                                                       (69.5% logic, 30.5% route)

TS11 minimum
8.267ns (data path)
  Source:               RAM1/_oe (FF)
  Destination:          _ram_oe (PAD)
  Requirement:          0.000ns
  Data Path Delay:      8.267ns (Levels of Logic = 1)

  Minimum Data Path: RAM1/_oe to _ram_oe
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X0Y26.YQ       Tcko                  0.576   _oe
                                                       RAM1/_oe
    P39.O1               net (fanout=1)        0.977   _oe
    P39.PAD              Tioop                 6.714   _ram_oe
                                                       &ram_oe_OBUF
                                                       _ram_oe
    -------------------------------------------------  ---------------------------
    Total                                      8.267ns (7.290ns logic, 0.977ns route)
                                                       (88.2% logic, 11.8% route)

TS20 maximum
22.537ns (requirement - data path)
  Source:               cpu_data<8> (PAD)
  Destination:          RAM1/write_data_8 (FF)
  Requirement:          33.000ns
  Data Path Delay:      10.463ns (Levels of Logic = 3)
  Destination Clock:    clk28m rising at 0.000ns

  Maximum Data Path: cpu_data<8> to RAM1/write_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P152.I               Tiopi                 1.918   cpu_data<8>
                                                       cpu_data<8>
                                                       cpu_data_8_IOBUF/IBUF
    SLICE_X27Y14.G1      net (fanout=22)       6.265   N953
    SLICE_X27Y14.Y       Tilo                  0.551   _l_data_11
                                                       gary_cpu_data_in<8>1
    SLICE_X28Y20.F2      net (fanout=3)        1.039   gary_cpu_data_in<8>
    SLICE_X28Y20.CLK     Tfck                  0.690   write_data_8
                                                       GARY1/ram_data_in<8>
                                                       RAM1/write_data_8
    -------------------------------------------------  ---------------------------
    Total                                     10.463ns (3.159ns logic, 7.304ns route)
                                                       (30.2% logic, 69.8% route)

TS20 minimum
5.078ns (data path)
  Source:               cpu_data<4> (PAD)
  Destination:          RAM1/write_data_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      5.078ns (Levels of Logic = 3)

  Minimum Data Path: cpu_data<4> to RAM1/write_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P166.I               Tiopi                 1.530   cpu_data<4>
                                                       cpu_data<4>
                                                       cpu_data_4_IOBUF/IBUF
    SLICE_X36Y16.F2      net (fanout=19)       2.479   N957
    SLICE_X36Y16.X       Tilo                  0.486   AGNUS1/cp1/ir2<11>
                                                       gary_cpu_data_in<4>1
    SLICE_X36Y19.F1      net (fanout=6)        0.477   gary_cpu_data_in<4>
    SLICE_X36Y19.CLK     Tckf        (-Th)    -0.106   write_data_4
                                                       GARY1/ram_data_in<4>
                                                       RAM1/write_data_4
    -------------------------------------------------  ---------------------------
    Total                                      5.078ns (2.122ns logic, 2.956ns route)
                                                       (41.8% logic, 58.2% route)

TS21 maximum
3.017ns (requirement - data path)
  Source:               CPU1/cache_data_selected (FF)
  Destination:          cpu_data<1> (PAD)
  Requirement:          16.000ns
  Data Path Delay:      12.983ns (Levels of Logic = 2)
  Source Clock:         cpu_clk_OBUF falling at 8.292ns

  Maximum Data Path: CPU1/cache_data_selected to cpu_data<1>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X47Y30.XQ      Tcko                  0.720   CPU1/cache_data_selected
                                                       CPU1/cache_data_selected
    SLICE_X46Y39.F2      net (fanout=19)       2.207   CPU1/cache_data_selected
    SLICE_X46Y39.X       Tilo                  0.608   PAULA1/pf1/dsktrack_2_0
                                                       CPU1/data_mux0000<1>1
    P154.O1              net (fanout=1)        2.442   cpu_data_1_IOBUF
    P154.PAD             Tioop                 7.006   cpu_data<1>
                                                       cpu_data_1_IOBUF/OBUFT
                                                       cpu_data<1>
    -------------------------------------------------  ---------------------------
    Total                                     12.983ns (8.334ns logic, 4.649ns route)
                                                       (64.2% logic, 35.8% route)

TS21 minimum
9.474ns (data path)
  Source:               CPU1/cache_data_held_8 (FF)
  Destination:          cpu_data<8> (PAD)
  Requirement:          0.000ns
  Data Path Delay:      9.474ns (Levels of Logic = 2)

  Minimum Data Path: CPU1/cache_data_held_8 to cpu_data<8>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X49Y29.YQ      Tcko                  0.576   CPU1/cache_data_held<8>
                                                       CPU1/cache_data_held_8
    SLICE_X49Y31.F3      net (fanout=1)        0.295   CPU1/cache_data_held<8>
    SLICE_X49Y31.X       Tilo                  0.441   AGNUS1/bl1/bltafwm<14>
                                                       CPU1/data_mux0000<8>1
    P152.O1              net (fanout=1)        1.448   cpu_data_8_IOBUF
    P152.PAD             Tioop                 6.714   cpu_data<8>
                                                       cpu_data_8_IOBUF/OBUFT
                                                       cpu_data<8>
    -------------------------------------------------  ---------------------------
    Total                                      9.474ns (7.731ns logic, 1.743ns route)
                                                       (81.6% logic, 18.4% route)

TS22 maximum
0.081ns (requirement - data path)
  Source:               CPU1/_ta_t (FF)
  Destination:          _cpu_dtack (PAD)
  Requirement:          5.750ns
  Data Path Delay:      5.669ns (Levels of Logic = 3)
  Source Clock:         cpu_clk_OBUF rising at 0.000ns

  Maximum Data Path: CPU1/_ta_t to _cpu_dtack
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X45Y40.YQ      Tcko                  0.720   CPU1/_ta_t
                                                       CPU1/_ta_t
    SLICE_X44Y43.G2      net (fanout=3)        0.714   CPU1/_ta_t
    SLICE_X44Y43.Y       Tilo                  0.608   CPU1/read_ack
                                                       CPU1/cpu_write_wait1
    SLICE_X45Y42.G2      net (fanout=1)        0.143   CPU1/cpu_write_wait
    SLICE_X45Y42.Y       Tilo                  0.551   PAULA1/pf1/selected_track<0>49
                                                       CPU1/_dtack1
    P138.O1              net (fanout=1)        1.291   &cpu_dtack_OBUF
    P138.PAD             Tioop                 1.642   _cpu_dtack
                                                       &cpu_dtack_OBUF
                                                       _cpu_dtack
    -------------------------------------------------  ---------------------------
    Total                                      5.669ns (3.521ns logic, 2.148ns route)
                                                       (62.1% logic, 37.9% route)

TS22 minimum
4.462ns (data path)
  Source:               CPU1/cache_hit_ack (FF)
  Destination:          _cpu_dtack (PAD)
  Requirement:          0.000ns
  Data Path Delay:      4.462ns (Levels of Logic = 3)

  Minimum Data Path: CPU1/cache_hit_ack to _cpu_dtack
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X45Y43.YQ      Tcko                  0.576   CPU1/cache_hit_ack
                                                       CPU1/cache_hit_ack
    SLICE_X45Y43.F3      net (fanout=2)        0.349   CPU1/cache_hit_ack
    SLICE_X45Y43.X       Tilo                  0.441   CPU1/cache_hit_ack
                                                       CPU1/cache_ack_guard1
    SLICE_X45Y42.G1      net (fanout=1)        0.272   CPU1/cache_ack_guard
    SLICE_X45Y42.Y       Tilo                  0.441   PAULA1/pf1/selected_track<0>49
                                                       CPU1/_dtack1
    P138.O1              net (fanout=1)        1.033   &cpu_dtack_OBUF
    P138.PAD             Tioop                 1.350   _cpu_dtack
                                                       &cpu_dtack_OBUF
                                                       _cpu_dtack
    -------------------------------------------------  ---------------------------
    Total                                      4.462ns (2.808ns logic, 1.654ns route)
                                                       (62.9% logic, 37.1% route)

TS23 maximum
12.359ns (requirement - data path)
  Source:               _cpu_uds (PAD)
  Destination:          CPU1/cache_lookup_hit (FF)
  Requirement:          20.000ns
  Data Path Delay:      7.641ns (Levels of Logic = 3)
  Destination Clock:    cpu_clk_OBUF falling at 8.292ns

  Maximum Data Path: _cpu_uds to CPU1/cache_lookup_hit
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P146.I               Tiopi                 1.918   _cpu_uds
                                                       _cpu_uds
                                                       &cpu_uds_IBUF
    SLICE_X52Y29.F3      net (fanout=5)        2.594   &cpu_uds_IBUF
    SLICE_X52Y29.X       Tilo                  0.608   full
                                                       CPU1/cache_lookup_hit_and0000_SW0
    SLICE_X51Y31.G4      net (fanout=1)        1.888   CPU1/N161
    SLICE_X51Y31.CLK     Tgck                  0.633   CPU1/cache_lookup_hit
                                                       CPU1/cache_lookup_hit_and0000
                                                       CPU1/cache_lookup_hit
    -------------------------------------------------  ---------------------------
    Total                                      7.641ns (3.159ns logic, 4.482ns route)
                                                       (41.3% logic, 58.7% route)

TS23 minimum
5.017ns (data path)
  Source:               _cpu_lds (PAD)
  Destination:          CPU1/cache_data_selected (FF)
  Requirement:          0.000ns
  Data Path Delay:      5.017ns (Levels of Logic = 3)

  Minimum Data Path: _cpu_lds to CPU1/cache_data_selected
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P143.I               Tiopi                 1.530   _cpu_lds
                                                       _cpu_lds
                                                       &cpu_lds_IBUF
    SLICE_X51Y28.F4      net (fanout=5)        1.594   &cpu_lds_IBUF
    SLICE_X51Y28.X       Tif5x                 0.729   AGNUS1/bltcon1_1
                                                       CPU1/cache_data_selected_mux000043_SW01
                                                       CPU1/cache_data_selected_mux000043_SW0_f5
    SLICE_X47Y30.BX      net (fanout=1)        1.047   CPU1/N1226
    SLICE_X47Y30.CLK     Tckdi       (-Th)    -0.117   CPU1/cache_data_selected
                                                       CPU1/cache_data_selected_mux000053_f5
                                                       CPU1/cache_data_selected
    -------------------------------------------------  ---------------------------
    Total                                      5.017ns (2.376ns logic, 2.641ns route)
                                                       (47.4% logic, 52.6% route)

TS24 maximum
2.205ns (requirement - data path)
  Source:               CPU1/read_data_held_9 (FF)
  Destination:          cpu_data<9> (PAD)
  Requirement:          16.000ns
  Data Path Delay:      13.795ns (Levels of Logic = 2)
  Source Clock:         clk rising at 0.000ns

  Maximum Data Path: CPU1/read_data_held_9 to cpu_data<9>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X31Y32.XQ      Tcko                  0.720   CPU1/read_data_held<9>
                                                       CPU1/read_data_held_9
    SLICE_X48Y33.G2      net (fanout=2)        2.862   CPU1/read_data_held<9>
    SLICE_X48Y33.Y       Tilo                  0.608   cpu_address_out<8>
                                                       CPU1/data_mux0000<9>1
    P149.O1              net (fanout=1)        2.599   cpu_data_9_IOBUF
    P149.PAD             Tioop                 7.006   cpu_data<9>
                                                       cpu_data_9_IOBUF/OBUFT
                                                       cpu_data<9>
    -------------------------------------------------  ---------------------------
    Total                                     13.795ns (8.334ns logic, 5.461ns route)
                                                       (60.4% logic, 39.6% route)

TS24 minimum
10.171ns (data path)
  Source:               CPU1/read_data_held_15 (FF)
  Destination:          cpu_data<15> (PAD)
  Requirement:          0.000ns
  Data Path Delay:      10.171ns (Levels of Logic = 2)

  Minimum Data Path: CPU1/read_data_held_15 to cpu_data<15>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X35Y33.XQ      Tcko                  0.576   CPU1/read_data_held<15>
                                                       CPU1/read_data_held_15
    SLICE_X49Y31.G2      net (fanout=2)        1.083   CPU1/read_data_held<15>
    SLICE_X49Y31.Y       Tilo                  0.441   AGNUS1/bl1/bltafwm<14>
                                                       CPU1/data_mux0000<15>1
    P135.O1              net (fanout=1)        1.357   cpu_data_15_IOBUF
    P135.PAD             Tioop                 6.714   cpu_data<15>
                                                       cpu_data_15_IOBUF/OBUFT
                                                       cpu_data<15>
    -------------------------------------------------  ---------------------------
    Total                                     10.171ns (7.731ns logic, 2.440ns route)
                                                       (76.0% logic, 24.0% route)

TS25 maximum
9.455ns (requirement - (data path - clock path skew + uncertainty))
  Source:               CPU1/read_data_held_1 (FF)
  Destination:          CPU1/Mram_cache_data_lo.A (RAM)
  Requirement:          16.000ns
  Data Path Delay:      6.545ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising
  Destination Clock:    cpu_clk_OBUF falling
  Clock Uncertainty:    0.000ns

  Maximum Data Path: CPU1/read_data_held_1 to CPU1/Mram_cache_data_lo.A
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y32.XQ      Tcko                  0.720   CPU1/read_data_held<1>
                                                       CPU1/read_data_held_1
    SLICE_X46Y23.G2      net (fanout=2)        2.721   CPU1/read_data_held<1>
    SLICE_X46Y23.Y       Tilo                  0.608   cpu_data_7_IOBUF
                                                       CPU1/cache_input_lo<1>1
    RAMB16_X1Y1.DIA1     net (fanout=1)        2.012   CPU1/cache_input_lo<1>
    RAMB16_X1Y1.CLKA     Tbdck                 0.484   CPU1/Mram_cache_data_lo
                                                       CPU1/Mram_cache_data_lo.A
    -------------------------------------------------  ---------------------------
    Total                                      6.545ns (1.812ns logic, 4.733ns route)
                                                       (27.7% logic, 72.3% route)

TS25 minimum
3.119ns (requirement - (clock path skew + uncertainty - data path))
  Source:               CPU1/read_data_held_10 (FF)
  Destination:          CPU1/Mram_cache_data_hi.A (RAM)
  Requirement:          0.000ns
  Data Path Delay:      3.119ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising
  Destination Clock:    cpu_clk_OBUF falling
  Clock Uncertainty:    0.000ns

  Minimum Data Path: CPU1/read_data_held_10 to CPU1/Mram_cache_data_hi.A
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X37Y31.XQ      Tcko                  0.576   CPU1/read_data_held<10>
                                                       CPU1/read_data_held_10
    SLICE_X48Y23.F4      net (fanout=2)        1.505   CPU1/read_data_held<10>
    SLICE_X48Y23.X       Tilo                  0.486   CPU1/cache_input_hi<2>
                                                       CPU1/cache_input_hi<2>1
    RAMB16_X1Y2.DIA2     net (fanout=1)        0.552   CPU1/cache_input_hi<2>
    RAMB16_X1Y2.CLKA     Tbckd       (-Th)     0.000   CPU1/Mram_cache_data_hi
                                                       CPU1/Mram_cache_data_hi.A
    -------------------------------------------------  ---------------------------
    Total                                      3.119ns (1.062ns logic, 2.057ns route)
                                                       (34.0% logic, 66.0% route)

TS_AUDIT_SRAM_DOE_HOLD maximum
20.255ns (requirement - data path)
  Source:               RAM1/doe_hold (FF)
  Destination:          ram_data<1> (PAD)
  Requirement:          33.000ns
  Data Path Delay:      12.745ns (Levels of Logic = 2)
  Source Clock:         clk28m falling at 17.621ns

  Maximum Data Path: RAM1/doe_hold to ram_data<1>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X7Y12.YQ       Tcko                  0.720   RAM1/doe_hold
                                                       RAM1/doe_hold
    SLICE_X5Y13.G2       net (fanout=1)        0.515   RAM1/doe_hold
    SLICE_X5Y13.Y        Tilo                  0.551   DENISE1/sprm0/sps1/datla<14>
                                                       RAM1/data_or0000_inv1
    P31.T1               net (fanout=16)       3.711   data_or0000_inv
    P31.PAD              Tiotp                 7.248   ram_data<1>
                                                       ram_data_1_IOBUF/OBUFT
                                                       ram_data<1>
    -------------------------------------------------  ---------------------------
    Total                                     12.745ns (8.519ns logic, 4.226ns route)
                                                       (66.8% logic, 33.2% route)

TS_AUDIT_SRAM_DOE_HOLD minimum
9.612ns (data path)
  Source:               RAM1/doe_hold (FF)
  Destination:          ram_data<12> (PAD)
  Requirement:          0.000ns
  Data Path Delay:      9.612ns (Levels of Logic = 2)

  Minimum Data Path: RAM1/doe_hold to ram_data<12>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X7Y12.YQ       Tcko                  0.576   RAM1/doe_hold
                                                       RAM1/doe_hold
    SLICE_X5Y13.G2       net (fanout=1)        0.412   RAM1/doe_hold
    SLICE_X5Y13.Y        Tilo                  0.441   DENISE1/sprm0/sps1/datla<14>
                                                       RAM1/data_or0000_inv1
    P46.T1               net (fanout=16)       1.275   data_or0000_inv
    P46.PAD              Tiotp                 6.908   ram_data<12>
                                                       ram_data_12_IOBUF/OBUFT
                                                       ram_data<12>
    -------------------------------------------------  ---------------------------
    Total                                      9.612ns (7.925ns logic, 1.687ns route)
                                                       (82.4% logic, 17.6% route)

TS_AUDIT_SRAM_WRITE_DATA maximum
21.421ns (requirement - data path)
  Source:               RAM1/write_data_3 (FF)
  Destination:          ram_data<3> (PAD)
  Requirement:          33.000ns
  Data Path Delay:      11.579ns (Levels of Logic = 1)
  Source Clock:         clk28m rising at 0.000ns

  Maximum Data Path: RAM1/write_data_3 to ram_data<3>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X35Y23.XQ      Tcko                  0.720   write_data_3
                                                       RAM1/write_data_3
    P34.O1               net (fanout=1)        3.853   write_data_3
    P34.PAD              Tioop                 7.006   ram_data<3>
                                                       ram_data_3_IOBUF/OBUFT
                                                       ram_data<3>
    -------------------------------------------------  ---------------------------
    Total                                     11.579ns (7.726ns logic, 3.853ns route)
                                                       (66.7% logic, 33.3% route)

TS_AUDIT_SRAM_WRITE_DATA minimum
9.066ns (data path)
  Source:               RAM1/write_data_5 (FF)
  Destination:          ram_data<5> (PAD)
  Requirement:          0.000ns
  Data Path Delay:      9.066ns (Levels of Logic = 1)

  Minimum Data Path: RAM1/write_data_5 to ram_data<5>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X31Y16.XQ      Tcko                  0.576   write_data_5
                                                       RAM1/write_data_5
    P67.O1               net (fanout=1)        1.776   write_data_5
    P67.PAD              Tioop                 6.714   ram_data<5>
                                                       ram_data_5_IOBUF/OBUFT
                                                       ram_data<5>
    -------------------------------------------------  ---------------------------
    Total                                      9.066ns (7.290ns logic, 1.776ns route)
                                                       (80.4% logic, 19.6% route)

TS_AUDIT_SRAM_RAM_CAPTURE maximum
14.294ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/aud1/Mram_audpt19 (RAM)
  Destination:          RAM1/write_data_9 (FF)
  Requirement:          35.242ns
  Data Path Delay:      20.574ns (Levels of Logic = 6)
  Clock Path Skew:      -0.020ns (1.804 - 1.824)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk28m rising at 35.242ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/aud1/Mram_audpt19 to RAM1/write_data_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y9.X        Tshcko                1.784   AGNUS1/address_aud<19>
                                                       AGNUS1/aud1/Mram_audpt19.WE
                                                       AGNUS1/aud1/Mram_audpt19
    SLICE_X23Y9.F2       net (fanout=2)        0.916   AGNUS1/address_aud<19>
    SLICE_X23Y9.X        Tilo                  0.551   DENISE1/sprm0/sps0/datla<12>
                                                       AGNUS1/address_out<19>4
    SLICE_X29Y14.F4      net (fanout=1)        3.181   AGNUS1/address_out<19>4
    SLICE_X29Y14.X       Tilo                  0.551   _l_data_7
                                                       AGNUS1/address_out<19>54
    SLICE_X20Y23.F2      net (fanout=5)        2.297   dma_address_out<19>
    SLICE_X20Y23.X       Tilo                  0.608   Mmux_bank218
                                                       BMAP1/Mmux_bank218
    SLICE_X21Y20.F1      net (fanout=2)        0.555   Mmux_bank218
    SLICE_X21Y20.X       Tilo                  0.551   profile_status<0>
                                                       BMAP1/Mmux_bank243
    SLICE_X17Y21.G1      net (fanout=1)        2.499   bank<0>
    SLICE_X17Y21.Y       Tilo                  0.551   DENISE1/sprm0/sps2/datla<15>
                                                       RAM1/enable81
    SLICE_X23Y17.F3      net (fanout=25)       1.731   enable_0
    SLICE_X23Y17.X       Tilo                  0.551   CLOCK1/profiles/want_sync<1>
                                                       RAM1/write_data_and00001
    SLICE_X26Y19.CE      net (fanout=16)       3.646   RAM1/write_data_and0000
    SLICE_X26Y19.CLK     Tceck                 0.602   write_data_9
                                                       RAM1/write_data_9
    -------------------------------------------------  ---------------------------
    Total                                     20.574ns (5.749ns logic, 14.825ns route)
                                                       (27.9% logic, 72.1% route)

TS_AUDIT_SRAM_RAM_CAPTURE minimum
3.405ns (requirement - (clock path skew + uncertainty - data path))
  Source:               PAULA1/pf1/db1/Mram_mem1.B (RAM)
  Destination:          RAM1/write_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.758ns (Levels of Logic = 2)
  Clock Path Skew:      -0.001ns (1.804 - 1.805)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk28m rising at 0.000ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: PAULA1/pf1/db1/Mram_mem1.B to RAM1/write_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB16_X1Y3.DOB3     Tbcko                 1.915   PAULA1/pf1/db1/Mram_mem1
                                                       PAULA1/pf1/db1/Mram_mem1.B
    SLICE_X35Y23.G4      net (fanout=3)        1.329   disk_dma_data<3>
    SLICE_X35Y23.Y       Tilo                  0.441   write_data_3
                                                       GARY1/ram_data_in<3>_SW0
    SLICE_X35Y23.F4      net (fanout=1)        0.012   GARY1/ram_data_in<3>_SW0/O
    SLICE_X35Y23.CLK     Tckf        (-Th)    -0.061   write_data_3
                                                       GARY1/ram_data_in<3>
                                                       RAM1/write_data_3
    -------------------------------------------------  ---------------------------
    Total                                      3.758ns (2.417ns logic, 1.341ns route)
                                                       (64.3% logic, 35.7% route)

TS_AUDIT_CPU_ADDRESS_CACHE_READ maximum
993.212ns (requirement - data path)
  Source:               cpu_address<7> (PAD)
  Destination:          CPU1/Mram_cache_data_lo.B (RAM)
  Requirement:          1000.000ns
  Data Path Delay:      6.788ns (Levels of Logic = 1)
  Destination Clock:    cpu_clk_OBUF falling at 8.292ns

  Maximum Data Path: cpu_address<7> to CPU1/Mram_cache_data_lo.B
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P101.I               Tiopi                 1.918   cpu_address<7>
                                                       cpu_address<7>
                                                       cpu_address_7_IBUF
    RAMB16_X1Y1.ADDRB9   net (fanout=5)        4.520   address<7>
    RAMB16_X1Y1.CLKB     Tback                 0.350   CPU1/Mram_cache_data_lo
                                                       CPU1/Mram_cache_data_lo.B
    -------------------------------------------------  ---------------------------
    Total                                      6.788ns (2.268ns logic, 4.520ns route)
                                                       (33.4% logic, 66.6% route)

TS_AUDIT_CPU_ADDRESS_CACHE_READ minimum
3.357ns (data path)
  Source:               cpu_address<10> (PAD)
  Destination:          CPU1/Mram_cache_data_lo.B (RAM)
  Requirement:          0.000ns
  Data Path Delay:      3.357ns (Levels of Logic = 1)

  Minimum Data Path: cpu_address<10> to CPU1/Mram_cache_data_lo.B
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P109.I               Tiopi                 1.530   cpu_address<10>
                                                       cpu_address<10>
                                                       cpu_address_10_IBUF
    RAMB16_X1Y1.ADDRB12  net (fanout=5)        1.827   address<10>
    RAMB16_X1Y1.CLKB     Tbcka       (-Th)     0.000   CPU1/Mram_cache_data_lo
                                                       CPU1/Mram_cache_data_lo.B
    -------------------------------------------------  ---------------------------
    Total                                      3.357ns (1.530ns logic, 1.827ns route)
                                                       (45.6% logic, 54.4% route)

TS_AUDIT_CPU_SRAM_READ_RETURN maximum
20.965ns (requirement - data path)
  Source:               ram_data<5> (PAD)
  Destination:          CPU1/read_data_held_5 (FF)
  Requirement:          33.000ns
  Data Path Delay:      12.035ns (Levels of Logic = 5)
  Destination Clock:    clk rising at 0.000ns

  Maximum Data Path: ram_data<5> to CPU1/read_data_held_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P67.I                Tiopi                 1.918   ram_data<5>
                                                       ram_data<5>
                                                       ram_data_5_IOBUF/IBUF
    SLICE_X28Y16.G2      net (fanout=1)        2.000   N940
    SLICE_X28Y16.Y       Tilo                  0.608   AGNUS1/bl1/bltadat<5>
                                                       RAM1/data_out<5>1
    SLICE_X28Y32.G4      net (fanout=4)        0.932   ram_data_out<5>
    SLICE_X28Y32.Y       Tilo                  0.608   PAULA1/pf1/spi_sdi_reg<14>
                                                       cpu_data_in<5>244_SW0
    SLICE_X34Y33.G1      net (fanout=1)        4.656   N1856
    SLICE_X34Y33.Y       Tilo                  0.608   CPU1/read_data_held<5>
                                                       cpu_data_in<5>281_SW0
    SLICE_X34Y33.F3      net (fanout=1)        0.015   cpu_data_in<5>281_SW0/O
    SLICE_X34Y33.CLK     Tfck                  0.690   CPU1/read_data_held<5>
                                                       cpu_data_in<5>281
                                                       CPU1/read_data_held_5
    -------------------------------------------------  ---------------------------
    Total                                     12.035ns (4.432ns logic, 7.603ns route)
                                                       (36.8% logic, 63.2% route)

TS_AUDIT_CPU_SRAM_READ_RETURN minimum
5.484ns (data path)
  Source:               ram_data<14> (PAD)
  Destination:          CPU1/read_data_held_14 (FF)
  Requirement:          0.000ns
  Data Path Delay:      5.484ns (Levels of Logic = 4)

  Minimum Data Path: ram_data<14> to CPU1/read_data_held_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P44.I                Tiopi                 1.530   ram_data<14>
                                                       ram_data<14>
                                                       ram_data_14_IOBUF/IBUF
    SLICE_X23Y24.F1      net (fanout=2)        1.973   N9311
    SLICE_X23Y24.X       Tilo                  0.441   N1636
                                                       cpu_data_in<14>339_SW0
    SLICE_X26Y33.G3      net (fanout=1)        0.936   N1636
    SLICE_X26Y33.Y       Tilo                  0.486   CPU1/read_data_held<14>
                                                       cpu_data_in<14>339_SW1_SW0
    SLICE_X26Y33.F3      net (fanout=1)        0.012   cpu_data_in<14>339_SW1_SW0/O
    SLICE_X26Y33.CLK     Tckf        (-Th)    -0.106   CPU1/read_data_held<14>
                                                       cpu_data_in<14>435
                                                       CPU1/read_data_held_14
    -------------------------------------------------  ---------------------------
    Total                                      5.484ns (2.563ns logic, 2.921ns route)
                                                       (46.7% logic, 53.3% route)
