TS_R7_CAPTURE_PERIOD setup
Slack (setup path):     3.250ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          CPU1/read_data_held_2 (FF)
  Requirement:          35.243ns
  Data Path Delay:      31.639ns (Levels of Logic = 17)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to CPU1/read_data_held_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y28.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.G2      net (fanout=1)        1.162   AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.Y       Tilo                  0.551   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y22.F3      net (fanout=6)        0.046   AGNUS1/N1_0
    SLICE_X29Y22.X       Tilo                  0.551   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X33Y22.F4      net (fanout=30)       0.833   dma_spr
    SLICE_X33Y22.X       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<4>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X31Y23.G1      net (fanout=29)       0.729   AGNUS1/N58
    SLICE_X31Y23.Y       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<5>
                                                       AGNUS1/dbr_and000073
    SLICE_X31Y23.F1      net (fanout=8)        0.566   AGNUS1/dbr_and0000
    SLICE_X31Y23.X       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<5>
                                                       AGNUS1/dbr
    SLICE_X33Y35.F3      net (fanout=38)       1.866   dbr
    SLICE_X33Y35.X       Tilo                  0.551   turbo
                                                       CPU1/enable114
    SLICE_X33Y34.G1      net (fanout=2)        0.352   CPU1/enable114
    SLICE_X33Y34.Y       Tilo                  0.551   PAULA1/pf1/spi_sdi_reg<12>
                                                       CPU1/enable
    SLICE_X28Y30.G2      net (fanout=7)        0.988   enable
    SLICE_X28Y30.Y       Tilo                  0.608   USERIO1/osd1/t_chipset_config<0>
                                                       CPU1/rd1
    SLICE_X30Y29.G4      net (fanout=48)       2.316   cpu_rd
    SLICE_X30Y29.Y       Tilo                  0.608   PAULA1/pf1/spi_sdi_reg<2>
                                                       AGNUS1/reg_address<1>1197
    SLICE_X30Y29.F2      net (fanout=1)        0.528   AGNUS1/reg_address<1>1197/O
    SLICE_X30Y29.X       Tilo                  0.608   PAULA1/pf1/spi_sdi_reg<2>
                                                       AGNUS1/reg_address<1>11118
    SLICE_X27Y24.G4      net (fanout=9)        1.548   AGNUS1/N31
    SLICE_X27Y24.Y       Tilo                  0.551   PAULA1/N2
                                                       AGNUS1/reg_address<6>74
    SLICE_X30Y35.G4      net (fanout=32)       4.864   reg_address<6>
    SLICE_X30Y35.Y       Tilo                  0.608   N2
                                                       PAULA1/pu1/data_out<13>11_SW0
    SLICE_X31Y41.G3      net (fanout=2)        1.080   PAULA1/pu1/N848
    SLICE_X31Y41.Y       Tilo                  0.551   USERIO1/osd1/osd_enable
                                                       PAULA1/pu1/data_out<13>11
    SLICE_X31Y41.F4      net (fanout=3)        0.018   PAULA1/pu1/N9
    SLICE_X31Y41.X       Tilo                  0.551   USERIO1/osd1/osd_enable
                                                       PAULA1/pu1/data_out<13>12
    SLICE_X35Y34.F3      net (fanout=14)       1.325   N2_0
    SLICE_X35Y34.X       Tilo                  0.551   PAULA1/dmacon<4>
                                                       cpu_data_in<2>247
    SLICE_X30Y32.F3      net (fanout=1)        2.604   cpu_data_in<2>247
    SLICE_X30Y32.X       Tilo                  0.608   tx_data_cnt_0
                                                       cpu_data_in<2>262
    SLICE_X33Y32.F4      net (fanout=1)        0.360   cpu_data_in<2>262
    SLICE_X33Y32.CLK     Tfck                  0.633   CPU1/read_data_held<2>
                                                       cpu_data_in<2>298
                                                       CPU1/read_data_held_2
    -------------------------------------------------  ---------------------------
    Total                                     31.639ns (10.454ns logic, 21.185ns route)
                                                       (33.0% logic, 67.0% route)

--------------------------------------------------------------------------------


TS_R7_CAPTURE_PERIOD hold
Slack (hold path):      1.788ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/dmacon_7 (FF)
  Destination:          CPU1/read_data_held_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.142ns (Levels of Logic = 2)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/dmacon_7 to CPU1/read_data_held_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X32Y23.YQ      Tcko                  0.576   dmacon_7
                                                       AGNUS1/dmacon_7
    SLICE_X32Y29.G4      net (fanout=3)        0.686   dmacon_7
    SLICE_X32Y29.Y       Tilo                  0.486   CPU1/read_data_held<7>
                                                       cpu_data_in<7>230
    SLICE_X32Y29.F4      net (fanout=1)        0.288   cpu_data_in<7>230/O
    SLICE_X32Y29.CLK     Tckf        (-Th)    -0.106   CPU1/read_data_held<7>
                                                       cpu_data_in<7>320
                                                       CPU1/read_data_held_7
    -------------------------------------------------  ---------------------------
    Total                                      2.142ns (1.168ns logic, 0.974ns route)
                                                       (54.5% logic, 45.5% route)

--------------------------------------------------------------------------------


TS_R7_SERVICE_PERIOD setup
Slack (setup path):     20.046ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          CPU1/read_complete (FF)
  Requirement:          35.243ns
  Data Path Delay:      14.843ns (Levels of Logic = 8)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to CPU1/read_complete
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y28.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.G2      net (fanout=1)        1.162   AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.Y       Tilo                  0.551   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y22.F3      net (fanout=6)        0.046   AGNUS1/N1_0
    SLICE_X29Y22.X       Tilo                  0.551   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X33Y22.F4      net (fanout=30)       0.833   dma_spr
    SLICE_X33Y22.X       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<4>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X31Y23.G1      net (fanout=29)       0.729   AGNUS1/N58
    SLICE_X31Y23.Y       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<5>
                                                       AGNUS1/dbr_and000073
    SLICE_X31Y23.F1      net (fanout=8)        0.566   AGNUS1/dbr_and0000
    SLICE_X31Y23.X       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<5>
                                                       AGNUS1/dbr
    SLICE_X33Y35.F3      net (fanout=38)       1.866   dbr
    SLICE_X33Y35.X       Tilo                  0.551   turbo
                                                       CPU1/enable114
    SLICE_X33Y34.G1      net (fanout=2)        0.352   CPU1/enable114
    SLICE_X33Y34.Y       Tilo                  0.551   PAULA1/pf1/spi_sdi_reg<12>
                                                       CPU1/enable
    SLICE_X28Y30.G2      net (fanout=7)        0.988   enable
    SLICE_X28Y30.Y       Tilo                  0.608   USERIO1/osd1/t_chipset_config<0>
                                                       CPU1/rd1
    SLICE_X43Y32.CE      net (fanout=48)       2.514   cpu_rd
    SLICE_X43Y32.CLK     Tceck                 0.602   CPU1/read_complete
                                                       CPU1/read_complete
    -------------------------------------------------  ---------------------------
    Total                                     14.843ns (5.787ns logic, 9.056ns route)
                                                       (39.0% logic, 61.0% route)

--------------------------------------------------------------------------------


TS_R7_SERVICE_PERIOD hold
Slack (hold path):      1.114ns (requirement - (clock path skew + uncertainty - data path))
  Source:               CPU1/read_as_seen (FF)
  Destination:          CPU1/read_serviced (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.468ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: CPU1/read_as_seen to CPU1/read_serviced
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X32Y34.YQ      Tcko                  0.576   CPU1/read_as_seen
                                                       CPU1/read_as_seen
    SLICE_X30Y31.SR      net (fanout=4)        0.863   CPU1/read_as_seen
    SLICE_X30Y31.CLK     Tcksr       (-Th)    -0.029   CPU1/read_serviced
                                                       CPU1/read_serviced
    -------------------------------------------------  ---------------------------
    Total                                      1.468ns (0.605ns logic, 0.863ns route)
                                                       (41.2% logic, 58.8% route)

--------------------------------------------------------------------------------


