TS_R4_COMPLETION equivalent PERIOD audit
214490 paths, 13 physical pins across four logical FFs; zero setup/hold errors.
Four destinations partitioned from chip7, with PERIOD TS_chip7 PHASE+0 HIGH50%; all other periods and SYSTEM_JITTER unchanged. Main PCF is unmodified.
Worst paths below are excerpts from completion.twr.

AGNUS1/bl1/busy: all setup
Slack (setup path):     7.289ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          AGNUS1/bl1/busy (FF)
  Requirement:          35.243ns
  Data Path Delay:      27.600ns (Levels of Logic = 13)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to AGNUS1/bl1/busy
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y28.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.G2      net (fanout=1)        1.162   AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.Y       Tilo                  0.551   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y22.F3      net (fanout=6)        0.046   AGNUS1/N1_0
    SLICE_X29Y22.X       Tilo                  0.551   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X33Y22.F4      net (fanout=30)       0.833   dma_spr
    SLICE_X33Y22.X       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<4>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X31Y23.G1      net (fanout=29)       0.729   AGNUS1/N58
    SLICE_X31Y23.Y       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<5>
                                                       AGNUS1/dbr_and000073
    SLICE_X31Y23.F1      net (fanout=8)        0.566   AGNUS1/dbr_and0000
    SLICE_X31Y23.X       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<5>
                                                       AGNUS1/dbr
    SLICE_X33Y35.F3      net (fanout=38)       1.866   dbr
    SLICE_X33Y35.X       Tilo                  0.551   turbo
                                                       CPU1/enable114
    SLICE_X33Y34.G1      net (fanout=2)        0.352   CPU1/enable114
    SLICE_X33Y34.Y       Tilo                  0.551   PAULA1/pf1/spi_sdi_reg<12>
                                                       CPU1/enable
    SLICE_X28Y30.G2      net (fanout=7)        0.988   enable
    SLICE_X28Y30.Y       Tilo                  0.608   USERIO1/osd1/t_chipset_config<0>
                                                       CPU1/rd1
    SLICE_X30Y29.G4      net (fanout=48)       2.316   cpu_rd
    SLICE_X30Y29.Y       Tilo                  0.608   PAULA1/pf1/spi_sdi_reg<2>
                                                       AGNUS1/reg_address<1>1197
    SLICE_X30Y29.F2      net (fanout=1)        0.528   AGNUS1/reg_address<1>1197/O
    SLICE_X30Y29.X       Tilo                  0.608   PAULA1/pf1/spi_sdi_reg<2>
                                                       AGNUS1/reg_address<1>11118
    SLICE_X24Y20.G1      net (fanout=9)        1.412   AGNUS1/N31
    SLICE_X24Y20.Y       Tilo                  0.608   DENISE1/col0/N8
                                                       AGNUS1/reg_address<3>96
    SLICE_X46Y17.F1      net (fanout=110)      4.852   reg_address<3>
    SLICE_X46Y17.X       Tilo                  0.608   AGNUS1/bl1/N27
                                                       AGNUS1/bl1/bltcon0_7_or000021
    SLICE_X49Y15.G2      net (fanout=10)       0.535   AGNUS1/bl1/N27
    SLICE_X49Y15.Y       Tilo                  0.551   AGNUS1/bl1/busy_or0000
                                                       AGNUS1/bl1/busy_or00001
    SLICE_X37Y18.BY      net (fanout=8)        2.078   AGNUS1/bl1/busy_or0000
    SLICE_X37Y18.CLK     Tsrck                 1.169   busy_0
                                                       AGNUS1/bl1/busy
    -------------------------------------------------  ---------------------------
    Total                                     27.600ns (9.337ns logic, 18.263ns route)
                                                       (33.8% logic, 66.2% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/busy: via_done setup
Slack (setup path):     23.988ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          AGNUS1/bl1/busy (FF)
  Requirement:          35.243ns
  Data Path Delay:      10.901ns (Levels of Logic = 6)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to AGNUS1/bl1/busy
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y28.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.G2      net (fanout=1)        1.162   AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.Y       Tilo                  0.551   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y22.F3      net (fanout=6)        0.046   AGNUS1/N1_0
    SLICE_X29Y22.X       Tilo                  0.551   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X33Y22.F4      net (fanout=30)       0.833   dma_spr
    SLICE_X33Y22.X       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<4>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X31Y23.G1      net (fanout=29)       0.729   AGNUS1/N58
    SLICE_X31Y23.Y       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<5>
                                                       AGNUS1/dbr_and000073
    SLICE_X31Y11.G2      net (fanout=8)        0.981   AGNUS1/dbr_and0000
    SLICE_X31Y11.Y       Tilo                  0.551   MIA1/magic_r_w<11>
                                                       AGNUS1/address_out<10>111
    SLICE_X36Y18.G1      net (fanout=24)       1.649   N33_1
    SLICE_X36Y18.Y       Tilo                  0.608   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X37Y18.CE      net (fanout=3)        0.816   int3
    SLICE_X37Y18.CLK     Tceck                 0.602   busy_0
                                                       AGNUS1/bl1/busy
    -------------------------------------------------  ---------------------------
    Total                                     10.901ns (4.685ns logic, 6.216ns route)
                                                       (43.0% logic, 57.0% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/busy: all hold
Slack (hold path):      2.326ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/bl1/blt_state_FSM_FFd4 (FF)
  Destination:          AGNUS1/bl1/busy (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.680ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/bl1/blt_state_FSM_FFd4 to AGNUS1/bl1/busy
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X35Y20.XQ      Tcko                  0.576   AGNUS1/blt_state_FSM_FFd4
                                                       AGNUS1/bl1/blt_state_FSM_FFd4
    SLICE_X36Y18.G4      net (fanout=10)       0.965   AGNUS1/blt_state_FSM_FFd4
    SLICE_X36Y18.Y       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X37Y18.CE      net (fanout=3)        0.653   int3
    SLICE_X37Y18.CLK     Tckce       (-Th)     0.000   busy_0
                                                       AGNUS1/bl1/busy
    -------------------------------------------------  ---------------------------
    Total                                      2.680ns (1.062ns logic, 1.618ns route)
                                                       (39.6% logic, 60.4% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/busy: via_done hold
Slack (hold path):      2.326ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/bl1/blt_state_FSM_FFd4 (FF)
  Destination:          AGNUS1/bl1/busy (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.680ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/bl1/blt_state_FSM_FFd4 to AGNUS1/bl1/busy
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X35Y20.XQ      Tcko                  0.576   AGNUS1/blt_state_FSM_FFd4
                                                       AGNUS1/bl1/blt_state_FSM_FFd4
    SLICE_X36Y18.G4      net (fanout=10)       0.965   AGNUS1/blt_state_FSM_FFd4
    SLICE_X36Y18.Y       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X37Y18.CE      net (fanout=3)        0.653   int3
    SLICE_X37Y18.CLK     Tckce       (-Th)     0.000   busy_0
                                                       AGNUS1/bl1/busy
    -------------------------------------------------  ---------------------------
    Total                                      2.680ns (1.062ns logic, 1.618ns route)
                                                       (39.6% logic, 60.4% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/start: all setup
Slack (setup path):     22.171ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          AGNUS1/bl1/start (FF)
  Requirement:          35.243ns
  Data Path Delay:      12.718ns (Levels of Logic = 7)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to AGNUS1/bl1/start
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y28.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.G2      net (fanout=1)        1.162   AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.Y       Tilo                  0.551   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y22.F3      net (fanout=6)        0.046   AGNUS1/N1_0
    SLICE_X29Y22.X       Tilo                  0.551   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X33Y22.F4      net (fanout=30)       0.833   dma_spr
    SLICE_X33Y22.X       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<4>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X31Y23.G1      net (fanout=29)       0.729   AGNUS1/N58
    SLICE_X31Y23.Y       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<5>
                                                       AGNUS1/dbr_and000073
    SLICE_X31Y11.G2      net (fanout=8)        0.981   AGNUS1/dbr_and0000
    SLICE_X31Y11.Y       Tilo                  0.551   MIA1/magic_r_w<11>
                                                       AGNUS1/address_out<10>111
    SLICE_X36Y18.G1      net (fanout=24)       1.649   N33_1
    SLICE_X36Y18.Y       Tilo                  0.608   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X36Y18.F2      net (fanout=3)        0.543   int3
    SLICE_X36Y18.X       Tilo                  0.608   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X40Y19.SR      net (fanout=2)        1.058   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X40Y19.CLK     Tsrck                 1.026   AGNUS1/bl1/start
                                                       AGNUS1/bl1/start
    -------------------------------------------------  ---------------------------
    Total                                     12.718ns (5.717ns logic, 7.001ns route)
                                                       (45.0% logic, 55.0% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/start: via_done setup
Slack (setup path):     22.171ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          AGNUS1/bl1/start (FF)
  Requirement:          35.243ns
  Data Path Delay:      12.718ns (Levels of Logic = 7)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to AGNUS1/bl1/start
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y28.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.G2      net (fanout=1)        1.162   AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.Y       Tilo                  0.551   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y22.F3      net (fanout=6)        0.046   AGNUS1/N1_0
    SLICE_X29Y22.X       Tilo                  0.551   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X33Y22.F4      net (fanout=30)       0.833   dma_spr
    SLICE_X33Y22.X       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<4>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X31Y23.G1      net (fanout=29)       0.729   AGNUS1/N58
    SLICE_X31Y23.Y       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<5>
                                                       AGNUS1/dbr_and000073
    SLICE_X31Y11.G2      net (fanout=8)        0.981   AGNUS1/dbr_and0000
    SLICE_X31Y11.Y       Tilo                  0.551   MIA1/magic_r_w<11>
                                                       AGNUS1/address_out<10>111
    SLICE_X36Y18.G1      net (fanout=24)       1.649   N33_1
    SLICE_X36Y18.Y       Tilo                  0.608   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X36Y18.F2      net (fanout=3)        0.543   int3
    SLICE_X36Y18.X       Tilo                  0.608   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X40Y19.SR      net (fanout=2)        1.058   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X40Y19.CLK     Tsrck                 1.026   AGNUS1/bl1/start
                                                       AGNUS1/bl1/start
    -------------------------------------------------  ---------------------------
    Total                                     12.718ns (5.717ns logic, 7.001ns route)
                                                       (45.0% logic, 55.0% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/start: all hold
Slack (hold path):      1.961ns (requirement - (clock path skew + uncertainty - data path))
  Source:               MIA1/rst_out (FF)
  Destination:          AGNUS1/bl1/start (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.315ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: MIA1/rst_out to AGNUS1/bl1/start
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X37Y19.YQ      Tcko                  0.576   mia_rst
                                                       MIA1/rst_out
    SLICE_X36Y18.F3      net (fanout=20)       0.377   mia_rst
    SLICE_X36Y18.X       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X40Y19.SR      net (fanout=2)        0.847   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X40Y19.CLK     Tcksr       (-Th)    -0.029   AGNUS1/bl1/start
                                                       AGNUS1/bl1/start
    -------------------------------------------------  ---------------------------
    Total                                      2.315ns (1.091ns logic, 1.224ns route)
                                                       (47.1% logic, 52.9% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/start: via_done hold
Slack (hold path):      3.470ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/bl1/blt_state_FSM_FFd4 (FF)
  Destination:          AGNUS1/bl1/start (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.824ns (Levels of Logic = 2)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/bl1/blt_state_FSM_FFd4 to AGNUS1/bl1/start
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X35Y20.XQ      Tcko                  0.576   AGNUS1/blt_state_FSM_FFd4
                                                       AGNUS1/bl1/blt_state_FSM_FFd4
    SLICE_X36Y18.G4      net (fanout=10)       0.965   AGNUS1/blt_state_FSM_FFd4
    SLICE_X36Y18.Y       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X36Y18.F2      net (fanout=3)        0.435   int3
    SLICE_X36Y18.X       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X40Y19.SR      net (fanout=2)        0.847   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X40Y19.CLK     Tcksr       (-Th)    -0.029   AGNUS1/bl1/start
                                                       AGNUS1/bl1/start
    -------------------------------------------------  ---------------------------
    Total                                      3.824ns (1.577ns logic, 2.247ns route)
                                                       (41.2% logic, 58.8% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/bltbold_init: all setup
Slack (setup path):     9.943ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          AGNUS1/bl1/bltbold_init (FF)
  Requirement:          35.243ns
  Data Path Delay:      24.946ns (Levels of Logic = 14)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to AGNUS1/bl1/bltbold_init
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y28.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.G2      net (fanout=1)        1.162   AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.Y       Tilo                  0.551   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y22.F3      net (fanout=6)        0.046   AGNUS1/N1_0
    SLICE_X29Y22.X       Tilo                  0.551   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X33Y22.F4      net (fanout=30)       0.833   dma_spr
    SLICE_X33Y22.X       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<4>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X31Y23.G1      net (fanout=29)       0.729   AGNUS1/N58
    SLICE_X31Y23.Y       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<5>
                                                       AGNUS1/dbr_and000073
    SLICE_X31Y23.F1      net (fanout=8)        0.566   AGNUS1/dbr_and0000
    SLICE_X31Y23.X       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<5>
                                                       AGNUS1/dbr
    SLICE_X33Y35.F3      net (fanout=38)       1.866   dbr
    SLICE_X33Y35.X       Tilo                  0.551   turbo
                                                       CPU1/enable114
    SLICE_X33Y34.G1      net (fanout=2)        0.352   CPU1/enable114
    SLICE_X33Y34.Y       Tilo                  0.551   PAULA1/pf1/spi_sdi_reg<12>
                                                       CPU1/enable
    SLICE_X28Y30.G2      net (fanout=7)        0.988   enable
    SLICE_X28Y30.Y       Tilo                  0.608   USERIO1/osd1/t_chipset_config<0>
                                                       CPU1/rd1
    SLICE_X30Y29.G4      net (fanout=48)       2.316   cpu_rd
    SLICE_X30Y29.Y       Tilo                  0.608   PAULA1/pf1/spi_sdi_reg<2>
                                                       AGNUS1/reg_address<1>1197
    SLICE_X30Y29.F2      net (fanout=1)        0.528   AGNUS1/reg_address<1>1197/O
    SLICE_X30Y29.X       Tilo                  0.608   PAULA1/pf1/spi_sdi_reg<2>
                                                       AGNUS1/reg_address<1>11118
    SLICE_X26Y22.G1      net (fanout=9)        1.434   AGNUS1/N31
    SLICE_X26Y22.Y       Tilo                  0.608   AGNUS1/bc1/N1042
                                                       AGNUS1/reg_address<8>61
    SLICE_X46Y17.G4      net (fanout=37)       2.704   reg_address<8>
    SLICE_X46Y17.Y       Tilo                  0.608   AGNUS1/bl1/N27
                                                       AGNUS1/bl1/address_generator_1/bltpth_3_or000021
    SLICE_X46Y19.G1      net (fanout=5)        0.564   AGNUS1/bl1/N5_0
    SLICE_X46Y19.Y       Tilo                  0.608   CPU1/cache_data_held<2>
                                                       AGNUS1/bl1/bltadat_cmp_eq000012
    SLICE_X46Y19.F3      net (fanout=4)        0.033   AGNUS1/bl1/N24
    SLICE_X46Y19.X       Tilo                  0.608   CPU1/cache_data_held<2>
                                                       AGNUS1/bl1/bltbdat_cmp_eq00001
    SLICE_X48Y22.CE      net (fanout=20)       1.390   AGNUS1/bl1/bltbdat_cmp_eq0000
    SLICE_X48Y22.CLK     Tceck                 0.602   AGNUS1/bl1/bltbold_init
                                                       AGNUS1/bl1/bltbold_init
    -------------------------------------------------  ---------------------------
    Total                                     24.946ns (9.435ns logic, 15.511ns route)
                                                       (37.8% logic, 62.2% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/bltbold_init: via_done setup
Slack (setup path):     21.682ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          AGNUS1/bl1/bltbold_init (FF)
  Requirement:          35.243ns
  Data Path Delay:      13.207ns (Levels of Logic = 7)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to AGNUS1/bl1/bltbold_init
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y28.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.G2      net (fanout=1)        1.162   AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.Y       Tilo                  0.551   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y22.F3      net (fanout=6)        0.046   AGNUS1/N1_0
    SLICE_X29Y22.X       Tilo                  0.551   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X33Y22.F4      net (fanout=30)       0.833   dma_spr
    SLICE_X33Y22.X       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<4>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X31Y23.G1      net (fanout=29)       0.729   AGNUS1/N58
    SLICE_X31Y23.Y       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<5>
                                                       AGNUS1/dbr_and000073
    SLICE_X31Y11.G2      net (fanout=8)        0.981   AGNUS1/dbr_and0000
    SLICE_X31Y11.Y       Tilo                  0.551   MIA1/magic_r_w<11>
                                                       AGNUS1/address_out<10>111
    SLICE_X36Y18.G1      net (fanout=24)       1.649   N33_1
    SLICE_X36Y18.Y       Tilo                  0.608   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X36Y18.F2      net (fanout=3)        0.543   int3
    SLICE_X36Y18.X       Tilo                  0.608   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X48Y22.SR      net (fanout=2)        1.547   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X48Y22.CLK     Tsrck                 1.026   AGNUS1/bl1/bltbold_init
                                                       AGNUS1/bl1/bltbold_init
    -------------------------------------------------  ---------------------------
    Total                                     13.207ns (5.717ns logic, 7.490ns route)
                                                       (43.3% logic, 56.7% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/bltbold_init: all hold
Slack (hold path):      2.353ns (requirement - (clock path skew + uncertainty - data path))
  Source:               MIA1/rst_out (FF)
  Destination:          AGNUS1/bl1/bltbold_init (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.706ns (Levels of Logic = 1)
  Clock Path Skew:      -0.001ns (0.295 - 0.296)
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: MIA1/rst_out to AGNUS1/bl1/bltbold_init
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X37Y19.YQ      Tcko                  0.576   mia_rst
                                                       MIA1/rst_out
    SLICE_X36Y18.F3      net (fanout=20)       0.377   mia_rst
    SLICE_X36Y18.X       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X48Y22.SR      net (fanout=2)        1.238   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X48Y22.CLK     Tcksr       (-Th)    -0.029   AGNUS1/bl1/bltbold_init
                                                       AGNUS1/bl1/bltbold_init
    -------------------------------------------------  ---------------------------
    Total                                      2.706ns (1.091ns logic, 1.615ns route)
                                                       (40.3% logic, 59.7% route)

--------------------------------------------------------------------------------


AGNUS1/bl1/bltbold_init: via_done hold
Slack (hold path):      3.862ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/bl1/blt_state_FSM_FFd4 (FF)
  Destination:          AGNUS1/bl1/bltbold_init (FF)
  Requirement:          0.000ns
  Data Path Delay:      4.215ns (Levels of Logic = 2)
  Clock Path Skew:      -0.001ns (0.295 - 0.296)
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/bl1/blt_state_FSM_FFd4 to AGNUS1/bl1/bltbold_init
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X35Y20.XQ      Tcko                  0.576   AGNUS1/blt_state_FSM_FFd4
                                                       AGNUS1/bl1/blt_state_FSM_FFd4
    SLICE_X36Y18.G4      net (fanout=10)       0.965   AGNUS1/blt_state_FSM_FFd4
    SLICE_X36Y18.Y       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X36Y18.F2      net (fanout=3)        0.435   int3
    SLICE_X36Y18.X       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X48Y22.SR      net (fanout=2)        1.238   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X48Y22.CLK     Tcksr       (-Th)    -0.029   AGNUS1/bl1/bltbold_init
                                                       AGNUS1/bl1/bltbold_init
    -------------------------------------------------  ---------------------------
    Total                                      4.215ns (1.577ns logic, 2.638ns route)
                                                       (37.4% logic, 62.6% route)

--------------------------------------------------------------------------------


PAULA1/pi1/intreq_6: all setup
Slack (setup path):     6.454ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          PAULA1/pi1/intreq_6 (FF)
  Requirement:          35.243ns
  Data Path Delay:      28.435ns (Levels of Logic = 15)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to PAULA1/pi1/intreq_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y28.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.G2      net (fanout=1)        1.162   AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.Y       Tilo                  0.551   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y22.F3      net (fanout=6)        0.046   AGNUS1/N1_0
    SLICE_X29Y22.X       Tilo                  0.551   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X33Y22.F4      net (fanout=30)       0.833   dma_spr
    SLICE_X33Y22.X       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<4>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X31Y23.G1      net (fanout=29)       0.729   AGNUS1/N58
    SLICE_X31Y23.Y       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<5>
                                                       AGNUS1/dbr_and000073
    SLICE_X31Y23.F1      net (fanout=8)        0.566   AGNUS1/dbr_and0000
    SLICE_X31Y23.X       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<5>
                                                       AGNUS1/dbr
    SLICE_X33Y35.F3      net (fanout=38)       1.866   dbr
    SLICE_X33Y35.X       Tilo                  0.551   turbo
                                                       CPU1/enable114
    SLICE_X33Y34.G1      net (fanout=2)        0.352   CPU1/enable114
    SLICE_X33Y34.Y       Tilo                  0.551   PAULA1/pf1/spi_sdi_reg<12>
                                                       CPU1/enable
    SLICE_X28Y30.G2      net (fanout=7)        0.988   enable
    SLICE_X28Y30.Y       Tilo                  0.608   USERIO1/osd1/t_chipset_config<0>
                                                       CPU1/rd1
    SLICE_X30Y29.G4      net (fanout=48)       2.316   cpu_rd
    SLICE_X30Y29.Y       Tilo                  0.608   PAULA1/pf1/spi_sdi_reg<2>
                                                       AGNUS1/reg_address<1>1197
    SLICE_X30Y29.F2      net (fanout=1)        0.528   AGNUS1/reg_address<1>1197/O
    SLICE_X30Y29.X       Tilo                  0.608   PAULA1/pf1/spi_sdi_reg<2>
                                                       AGNUS1/reg_address<1>11118
    SLICE_X27Y24.G4      net (fanout=9)        1.548   AGNUS1/N31
    SLICE_X27Y24.Y       Tilo                  0.551   PAULA1/N2
                                                       AGNUS1/reg_address<6>74
    SLICE_X30Y35.G4      net (fanout=32)       4.864   reg_address<6>
    SLICE_X30Y35.Y       Tilo                  0.608   N2
                                                       PAULA1/pu1/data_out<13>11_SW0
    SLICE_X30Y35.F2      net (fanout=2)        0.562   PAULA1/pu1/N848
    SLICE_X30Y35.X       Tilo                  0.608   N2
                                                       PAULA1/pi1/intena_cmp_eq00001
    SLICE_X30Y37.G1      net (fanout=5)        0.546   N2
    SLICE_X30Y37.Y       Tilo                  0.608   PAULA1/pi1/N887
                                                       PAULA1/pi1/tmp_cmp_eq00001
    SLICE_X36Y28.G2      net (fanout=15)       2.063   PAULA1/pi1/tmp_cmp_eq0000
    SLICE_X36Y28.CLK     Tgck                  0.690   intreq_6
                                                       PAULA1/pi1/intreq_6_or00001
                                                       PAULA1/pi1/intreq_6
    -------------------------------------------------  ---------------------------
    Total                                     28.435ns (9.466ns logic, 18.969ns route)
                                                       (33.3% logic, 66.7% route)

--------------------------------------------------------------------------------


PAULA1/pi1/intreq_6: via_done setup
Slack (setup path):     22.917ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          PAULA1/pi1/intreq_6 (FF)
  Requirement:          35.243ns
  Data Path Delay:      11.972ns (Levels of Logic = 6)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to PAULA1/pi1/intreq_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y28.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.G2      net (fanout=1)        1.162   AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.Y       Tilo                  0.551   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y22.F3      net (fanout=6)        0.046   AGNUS1/N1_0
    SLICE_X29Y22.X       Tilo                  0.551   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X33Y22.F4      net (fanout=30)       0.833   dma_spr
    SLICE_X33Y22.X       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<4>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X31Y23.G1      net (fanout=29)       0.729   AGNUS1/N58
    SLICE_X31Y23.Y       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<5>
                                                       AGNUS1/dbr_and000073
    SLICE_X31Y11.G2      net (fanout=8)        0.981   AGNUS1/dbr_and0000
    SLICE_X31Y11.Y       Tilo                  0.551   MIA1/magic_r_w<11>
                                                       AGNUS1/address_out<10>111
    SLICE_X36Y18.G1      net (fanout=24)       1.649   N33_1
    SLICE_X36Y18.Y       Tilo                  0.608   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X36Y28.BY      net (fanout=3)        1.320   int3
    SLICE_X36Y28.CLK     Tsrck                 1.169   intreq_6
                                                       PAULA1/pi1/intreq_6
    -------------------------------------------------  ---------------------------
    Total                                     11.972ns (5.252ns logic, 6.720ns route)
                                                       (43.9% logic, 56.1% route)

--------------------------------------------------------------------------------


PAULA1/pi1/intreq_6: all hold
Slack (hold path):      1.029ns (requirement - (clock path skew + uncertainty - data path))
  Source:               PAULA1/pi1/intreq_6 (FF)
  Destination:          PAULA1/pi1/intreq_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.029ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: PAULA1/pi1/intreq_6 to PAULA1/pi1/intreq_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y28.YQ      Tcko                  0.576   intreq_6
                                                       PAULA1/pi1/intreq_6
    SLICE_X36Y28.G3      net (fanout=3)        0.347   intreq_6
    SLICE_X36Y28.CLK     Tckg        (-Th)    -0.106   intreq_6
                                                       PAULA1/pi1/intreq_6_or00001
                                                       PAULA1/pi1/intreq_6
    -------------------------------------------------  ---------------------------
    Total                                      1.029ns (0.682ns logic, 0.347ns route)
                                                       (66.3% logic, 33.7% route)

--------------------------------------------------------------------------------



PAULA1/pi1/intreq_6: via_done hold
Slack (hold path):      2.872ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/bl1/blt_state_FSM_FFd4 (FF)
  Destination:          PAULA1/pi1/intreq_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.226ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         clk rising at 140.968ns
  Destination Clock:    clk rising at 140.968ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/bl1/blt_state_FSM_FFd4 to PAULA1/pi1/intreq_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X35Y20.XQ      Tcko                  0.576   AGNUS1/blt_state_FSM_FFd4
                                                       AGNUS1/bl1/blt_state_FSM_FFd4
    SLICE_X36Y18.G4      net (fanout=10)       0.965   AGNUS1/blt_state_FSM_FFd4
    SLICE_X36Y18.Y       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X36Y28.BY      net (fanout=3)        1.056   int3
    SLICE_X36Y28.CLK     Tcksr       (-Th)    -0.143   intreq_6
                                                       PAULA1/pi1/intreq_6
    -------------------------------------------------  ---------------------------
    Total                                      3.226ns (1.205ns logic, 2.021ns route)
                                                       (37.4% logic, 62.6% route)

--------------------------------------------------------------------------------


Related clk28 via_done: reported setup
Slack (setup path):     21.682ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AGNUS1/spr1/sprdmastate (FF)
  Destination:          AGNUS1/bl1/bltbold_init (FF)
  Requirement:          35.243ns
  Data Path Delay:      13.207ns (Levels of Logic = 7)
  Clock Path Skew:      0.000ns
  Source Clock:         clk28m rising at 387.662ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AGNUS1/spr1/sprdmastate to AGNUS1/bl1/bltbold_init
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y28.YQ      Tcko                  0.720   AGNUS1/spr1/sprdmastate
                                                       AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.G2      net (fanout=1)        1.162   AGNUS1/spr1/sprdmastate
    SLICE_X29Y22.Y       Tilo                  0.551   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y22.F3      net (fanout=6)        0.046   AGNUS1/N1_0
    SLICE_X29Y22.X       Tilo                  0.551   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X33Y22.F4      net (fanout=30)       0.833   dma_spr
    SLICE_X33Y22.X       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<4>
                                                       AGNUS1/bl1/blt_state_FSM_FFd4-In1
    SLICE_X31Y23.G1      net (fanout=29)       0.729   AGNUS1/N58
    SLICE_X31Y23.Y       Tilo                  0.551   DENISE1/sprm0/sps0/datlb<5>
                                                       AGNUS1/dbr_and000073
    SLICE_X31Y11.G2      net (fanout=8)        0.981   AGNUS1/dbr_and0000
    SLICE_X31Y11.Y       Tilo                  0.551   MIA1/magic_r_w<11>
                                                       AGNUS1/address_out<10>111
    SLICE_X36Y18.G1      net (fanout=24)       1.649   N33_1
    SLICE_X36Y18.Y       Tilo                  0.608   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X36Y18.F2      net (fanout=3)        0.543   int3
    SLICE_X36Y18.X       Tilo                  0.608   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/bltbold_init_or00001
    SLICE_X48Y22.SR      net (fanout=2)        1.547   AGNUS1/bl1/bltbold_init_or0000
    SLICE_X48Y22.CLK     Tsrck                 1.026   AGNUS1/bl1/bltbold_init
                                                       AGNUS1/bl1/bltbold_init
    -------------------------------------------------  ---------------------------
    Total                                     13.207ns (5.717ns logic, 7.490ns route)
                                                       (43.3% logic, 56.7% route)

--------------------------------------------------------------------------------


Related clk28 via_done: reported hold
Slack (hold path):      6.153ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AGNUS1/spr1/sprvstop (FF)
  Destination:          AGNUS1/bl1/busy (FF)
  Requirement:          -0.001ns
  Data Path Delay:      6.509ns (Levels of Logic = 4)
  Clock Path Skew:      0.001ns (1.805 - 1.804)
  Source Clock:         clk28m rising at 422.904ns
  Destination Clock:    clk rising at 422.905ns
  Clock Uncertainty:    0.354ns

  Clock Uncertainty:          0.354ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.707ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: AGNUS1/spr1/sprvstop to AGNUS1/bl1/busy
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X28Y22.YQ      Tcko                  0.576   AGNUS1/sprvstop
                                                       AGNUS1/spr1/sprvstop
    SLICE_X29Y22.G4      net (fanout=2)        0.298   AGNUS1/sprvstop
    SLICE_X29Y22.Y       Tilo                  0.441   dma_spr
                                                       AGNUS1/spr1/reg_address_out<1>11
    SLICE_X29Y22.F3      net (fanout=6)        0.037   AGNUS1/N1_0
    SLICE_X29Y22.X       Tilo                  0.441   dma_spr
                                                       AGNUS1/dma_spr1
    SLICE_X31Y11.G1      net (fanout=30)       1.816   dma_spr
    SLICE_X31Y11.Y       Tilo                  0.441   MIA1/magic_r_w<11>
                                                       AGNUS1/address_out<10>111
    SLICE_X36Y18.G1      net (fanout=24)       1.320   N33_1
    SLICE_X36Y18.Y       Tilo                  0.486   AGNUS1/bl1/bltbold_init_or0000
                                                       AGNUS1/bl1/done
    SLICE_X37Y18.CE      net (fanout=3)        0.653   int3
    SLICE_X37Y18.CLK     Tckce       (-Th)     0.000   busy_0
                                                       AGNUS1/bl1/busy
    -------------------------------------------------  ---------------------------
    Total                                      6.509ns (2.385ns logic, 4.124ns route)
                                                       (36.6% logic, 63.4% route)

--------------------------------------------------------------------------------
